Multiple layer and crystal plane orientation semiconductor substrate
AssigneeInternational Business Machines Corporation
InventorsToshiharu Furukawa, David Horak, Charles Koburger, Leathen Shi
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Abstract
A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
Claims30
A substrate, comprising:
- a first crystalline semiconductor layer and a second crystalline semiconductor layer;
- and
- an insulating layer bonding a bottom surface of said first crystalline semiconductor layer to a top surface of said second crystalline semiconductor layer, a first crystal direction of said first crystalline semiconductor layer aligned relative to a second crystal direction of said second crystalline semiconductor layer, said first crystal direction different from said second crystal direction.
A method of fabricating a substrate, comprising:
- providing a first crystalline semiconductor substrate, providing a second crystalline semiconductor substrate;
- aligning a first crystal direction of said first crystalline semiconductor substrate to a second crystal direction of said second crystalline semiconductor substrate, said first crystal direction different from said second crystal direction;
- and
- forming an insulating layer between a bottom surface of said first crystalline semiconductor substrate and a top surface of said second crystalline semiconductor substrate, said insulating layer bonding said first crystalline semiconductor substrate to said second crystalline semiconductor substrate.
An integrated circuit chip, comprising:
- a first crystalline semiconductor layer and a second crystalline semiconductor layer;
- an insulating layer bonding a bottom surface of said first crystalline semiconductor layer to a top surface of said second crystalline semiconductor layer, a first crystal direction of said first crystalline semiconductor layer aligned relative to a second crystal direction of said second crystalline semiconductor layer, said first crystal direction different from said second crystal direction;
- a field effect transistor comprising a source region, a drain region and a channel region separating said source and drain regions, said source, drain and a channel regions formed in said first crystalline semiconductor layer, a lengthwise direction of said channel extending between said source and drain regions aligned with both said first and said second directions;
- and at least one edge of said integrated circuit chip aligned with said second direction.
A method of fabricating an integrated circuit chip, comprising:
- providing a semiconductor-on-insulator substrate comprising a first crystalline semiconductor layer and a second crystalline semiconductor layer, a first crystal direction of said first crystalline semiconductor substrate aligned relative to a second crystal direction of said second crystalline semiconductor substrate, said first crystal direction different from said second crystal direction, an insulating layer formed between a bottom surface of said first crystalline semiconductor substrate and a top surface of said second crystalline semiconductor substrate, said insulating layer bonding said first crystalline semiconductor substrate to said second crystalline semiconductor;
- forming a field effect transistor comprising a source region, a drain region and a channel region separating said source and drain regions, said source, drain and a channel regions formed in said first crystalline semiconductor layer, a lengthwise direction of said channel extending between said source and drain regions aligned with both said first and said second directions;
- and dicing said semiconductor-on-insulator substrate along said second direction to form at least one edge of said integrated circuit chip.
Dependencies are inferred from the claim text.