Method and apparatus for efficient and flexible sequencing of data processing units extending VLIW architecture

A processor comprising:

• a) a plurality of functional units, each having a control input;
• b) a sequencer having an instruction input with a plurality of fields, each field capable of having a value, and a plurality of control outputs, each control output coupled to a control input of a functional unit, the sequencer comprising:
• i) a timing circuit having an output defining a plurality cycles;
• ii) logic to generate, during a cycle, values of the control outputs in response to the values of a first portion of the plurality of fields of the instruction input;
• and
• iii) flow control logic comprising an iteration counter capable of having a value, the iteration counter coupled to receive a value based on a value in a second portion of the plurality of fields of the instruction input, the flow control logic coupled to the logic to generate values to control the logic to generate values to repeat the generated values during a number of cycles determined by the value received from the second portion of the plurality of fields of the instruction input.

A method of operating a disk controller comprising:

• a) sensing recording media to produce a signal;
• b) providing the signal to a plurality of functional units each having a control input with the plurality of functional units having an output;
• c) reading an instruction from a memory;
• and
• d) generating control inputs to the plurality of functional units during at least a cycle of operation of the disk controller based on the instruction read from memory.