# US 2006/0154469 A1 · Method and apparatus for providing structural support for interconnect pad while allowing signal conductance

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- Number: US 2006/0154469 A1
- Document ID: US20060154469A1
- Status: Published application
- Kind: A1
- Application number: 11/033,008
- Filed: 2005-01-11
- Published: 2006-07-13
- Earliest claimed: 2005-01-11
- Assignees: Freescale Semiconductor, Inc.
- Inventors: Kevin Hess; Susan Downey; James Miller; Cheng Yong
- Web page: https://patentgrep.com/patent/US20060154469A1

## CPC

- H10W 72/019: {of bond pads}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/4421: {the principal metal being copper}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.

## Claims

### Claim 1

A method for providing structural support for an interconnect pad, the method comprising:
providing a substrate;
providing a first metal layer overlying the substrate, the first metal layer having a plurality of openings;
providing a first electrically insulating layer overlying the first metal layer;
providing a second metal layer overlying the first electrically insulating layer, the second metal layer having a plurality of openings;
providing an interconnect pad overlying the second metal layer, the interconnect pad defining an interconnect pad area;
creating a physical layout shape from a logic operation on the first metal layer and the second metal layer;
determining a value X which is a metal density of the physical layout shape within a region of the interconnect pad; and
using the value X to determine if sufficient alignment of the plurality of openings of the first metal layer and the plurality of openings of the second metal layer exist for sufficient structural support.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
requiring the value X to be less than or equal to a predetermined threshold.

### Claim 3 (depends on 2)

The method of claim 2 wherein the predetermined threshold comprises 0.85.

### Claim 4 (depends on 2)

The method of claim 2 wherein the predetermined threshold comprises a range from 0.80 to 0.85, inclusive.

### Claim 5 (depends on 2)

The method of claim 2 wherein the predetermined threshold comprises a range from 0.70 to 0.95, inclusive.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
providing a second electrically insulating layer overlying the second metal layer; and
providing a third metal layer interposed between the second electrically insulating layer and the interconnect pad, the third metal layer having a plurality of openings.

### Claim 7 (depends on 6)

The method of claim 6 wherein the first electrically insulating layer and the second electrically insulating layer comprise a same material.

### Claim 8 (depends on 1)

The method of claim 1 wherein the first electrically insulating layer comprises a dielectric.

### Claim 9 (depends on 1)

The method of claim 1 wherein the first electrically insulating layer has a permittivity less than 4.

### Claim 10 (depends on 1)

The method of claim 1, wherein the first electrically insulating layer has a modulus value less than 80 gigaPascals.

### Claim 11 (depends on 1)

The method of claim 1, wherein the plurality of openings in the first metal layer and the plurality of openings in the second metal layer are substantially filled with the first electrically insulating layer.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first metal layer and the second metal layer respectively have a physical metal density in a range of 20-80% for respective areas of the first metal layer and the second metal layer.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
providing one or more vias through the first electrically insulating layer to electrically connect at least a portion of the first metal layer to at least a portion of the second metal layer.

### Claim 14 (depends on 1)

The method of claim 1, further comprising:
providing a passivation layer interposed between the interconnect pad and the second metal layer.

### Claim 15 (depends on 1)

The method of claim 1 wherein at least one device is formed in the substrate underlying the interconnect pad.

### Claim 16

An interconnect pad structure formed within an interconnect pad region comprising:
a substrate having semiconductor devices formed therein; and
a plurality of conductive layers, each overlying the substrate within the interconnect pad region and in contact with one or more low modulus dielectric material(s), the plurality of conductive layers being formed with vertically aligned openings over a predetermined portion of the interconnect pad region sufficient to provide mechanical support for the interconnect pad structure.

### Claim 17 (depends on 16)

The interconnect pad structure of claim 16 further comprising:
a dielectric layer overlying an uppermost of the plurality of conductive layers, the dielectric layer comprising a region with no metal density within the region of the dielectric layer thereby having no metal passing through any opening of the dielectric layer, the region occupying at least fifty percent of the interconnect pad region; and
a conductive interconnect pad layer overlying the dielectric layer.

### Claim 18

An interconnect pad structure formed within an interconnect pad region comprising:
a substrate and active circuitry functionally using the substrate;
a plurality of metal interconnect layers overlying the substrate, the plurality of metal interconnect layers being in contact with one or more low modulus dielectric materials and formed with vertically aligned openings within a predetermined portion of the interconnect pad region;
an uppermost metal interconnect layer overlying the plurality of metal interconnect layers;
an insulating layer overlying the uppermost metal interconnect layer and having one or more openings to expose a first electrical conductor of the uppermost metal interconnect layer; and
a conductive pad formed overlying the insulating layer and connected to the first electrical conductor by filling the one or more openings, wherein a second electrical conductor of the uppermost metal interconnect layer is electrically isolated from the conductive pad only by the insulating layer and the second electrical conductor is not directly connected to the conductive pad, the first electrical conductor and the second electrical conductor being separated by a dielectric material having a modulus greater than that of the one or more low modulus dielectric materials.

### Claim 19 (depends on 18)

The interconnect pad structure of claim 18 wherein an opening in the uppermost metal interconnect layer that separates the first electrical conductor of the uppermost metal interconnect layer from the second electrical conductor of the uppermost metal interconnect layer is not fully aligned with the vertically aligned openings of the plurality of metal interconnect layers.

### Claim 20

An interconnect pad structure within an interconnect pad region comprising:
a substrate having active circuitry;
a plurality of metal interconnect layers overlying the substrate, each of the plurality of metal interconnect layers being in contact with one or more low modulus dielectric materials and formed with vertically aligned openings within a predetermined portion of the interconnect pad region;
an insulating layer overlying the plurality of metal interconnect layers; and
a metal pad formed overlying the insulating layer and connected to a first electrical conductor of an uppermost one of the plurality of metal interconnect layers by filling one or more openings in the insulating layer, wherein a second electrical conductor of the uppermost one of the plurality of metal interconnect layers is electrically isolated from the metal pad only by the insulating layer and the second electrical conductor is not directly connected to the metal pad.