# US 2006/0154409 A1 · Method for fabricating non-volatile memory

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- Number: US 2006/0154409 A1
- Document ID: US20060154409A1
- Status: Published application
- Kind: A1
- Application number: 11/162,833
- Filed: 2005-09-26
- Published: 2006-07-13
- Earliest claimed: 2005-01-11
- Assignees: Powerchip Semiconductor Corp.
- Inventors: Saysamone Pittikoun
- Web page: https://patentgrep.com/patent/US20060154409A1

## CPC

- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/691: {having more than two programming levels}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a non-volatile memory is described. A substrate is provided and a first dielectric layer, an electron trapping layer and a second dielectric layer are sequentially formed thereon. Each of the stacked gate structures includes a first gate and a cap layer having a gap between every two stacked gate structures. An oxide layer is formed on the sidewalls of the first gate. A portion of the second dielectric layer not covered by the stacked gate structures is removed. A third dielectric layer is further formed on the substrate. A second conductive layer is formed over the substrate, and a portion thereof to form second gates. The second gates and the stacked gate structures form a column of memory cells. A source region and a drain region are formed in the substrate adjacent to two sides of the column of memory cells.

## Claims

### Claim 1

A fabrication method of a non-volatile memory, the fabrication method of a non-volatile memory comprising:
forming a first dielectric layer over a substrate;
forming a charge trapping layer;
forming a second dielectric layer;
forming a plurality of stacked gate structures above the second dielectric layer, wherein each stacked gate structures further comprises a first gate and every two of the adjacent stacked gate structures comprises a gap there between;
removing the second dielectric layer not covered by the stacked gate structures to expose the charge trapping layer;
forming a third dielectric layer to cover a surface of the stacked gate structures and the exposed surface of the charge trapping layer;
forming a second conducting layer above the substrate;
removing a portion of the second conducting layer to form a plurality of second gates which each fills the gap between the stacked gate structures, and the second gates and the stacked gate structures form a column of memory cells; and
forming a source region and a drain region beside two sides of the column of memory cells in the substrate.

### Claim 2 (depends on 2)

The fabrication method for the non-volatile memory as recited in claim 2, wherein each stacked gate structure further comprises a cap layer disposed above the first gate.

### Claim 3 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein the step of forming the plurality of the stacked gate structures above the second dielectric layer comprises:
forming a first conducting layer over the second dielectric layer;
forming an insulating layer above the first conducting layer; and
patterning both the insulating layer and the first conducting layer to form the cap layers and the first gates.

### Claim 4 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1 further comprises a step of forming a fourth dielectric layer on side walls of the first gate.

### Claim 5 (depends on 4)

The fabrication method for the non-volatile memory as recited in claim 4, wherein the formation of the fourth dielectric layer comprises a thermal oxidation process.

### Claim 6 (depends on 4)

The fabrication method for the non-volatile memory as recited in claim 4, wherein a material constituting the fourth dielectric layer comprises silicon oxide.

### Claim 7 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, where the step for removing the portion of the second dielectric layer not covered by the stacked gate structures comprises a dry etching process.

### Claim 8 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein the step for forming the first dielectric layer comprises of a thermal oxidation process.

### Claim 9 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein the step for forming the charge trapping layer above the first dielectric layer comprises a chemical vapor deposition process.

### Claim 10 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein the step for forming the second dielectric layer above the charge trapping layer comprises a chemical vapor deposition process.

### Claim 11 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein the step for forming the second conducting layer above the substrate comprises performing a chemical vapor deposition process.

### Claim 12 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein the step for removing the portion of the second conducting layer comprises performing a dry etching process or a chemical mechanical polishing process.

### Claim 13 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein the step for forming a source region and drain region comprises an ion implantation process.

### Claim 14 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein a material constituting the first dielectric layer comprises silicon oxide.

### Claim 15 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein a material constituting the charge trapping layer comprises silicon nitride.

### Claim 16 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein a material constituting the second dielectric layer comprises silicon oxide.

### Claim 17 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein a material constituting the third dielectric layer comprises silicon oxide.

### Claim 18 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, where a material constituting the first conducting layer comprises doped polysilicon.

### Claim 19 (depends on 1)

The fabrication method for the non-volatile memory as recited in claim 1, wherein a material constituting the second conducting layer comprises doped polysilicon.