# US 2006/0152289 A1 · Variable lock-in circuit for phase-locked loops > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2006/0152289 A1 - Document ID: US20060152289A1 - Status: Published application - Kind: A1 - Application number: 11/034,341 - Filed: 2005-01-11 - Published: 2006-07-13 - Earliest claimed: 2005-01-11 - Assignees: ANA Semiconductor - Inventors: Sangbeom Park - Web page: https://patentgrep.com/patent/US20060152289A1 ## CPC - H03L 7/107: using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth - H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump} - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - Y10S 331/02: Phase locked loop having lock indicating or detecting means - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ## Abstract The variable lock-in circuits basically include a sensor, triggering transistors, current mirror, current source, an N-bit triggering circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the triggering transistors, which provide a total current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor. Consequently, all variable lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule. ## Claims ### Claim 1 A variable lock-in circuit for enabling any phase-locked loop to be locked according to schedule, comprising: a feedback line connected with the output and input of the variable lock-in circuit and also coupled to the output of a filter; a sensor for sensing a voltage at the output, comparing with the midpoint voltage decided by the device aspect ratios of the sensor, and providing its output; an N-bit binary-weighted triggering circuit array with the base triggering transistor for generating a total current corresponding to an N-bit digital input and an output of the sensor; a current mirror for receiving the total current and providing the total current to the output; and a current source coupled to the output. ### Claim 2 (depends on 1) The circuit as recited in claim 1 wherein the sensor is inverter. ### Claim 3 (depends on 1) The circuit as recited in claim 1 wherein the sensor is comparator. ### Claim 4 (depends on 1) The circuit as recited in claim 1 wherein the sensor is operational amplifier. ### Claim 5 (depends on 1) The circuit as recited in claim 1 wherein the sensor is CMOS NAND gate since the two-input CMOS NAND gate can be used as an enabling inverter with one input serving as an active high enable input and the other used as the logical input. ### Claim 6 (depends on 1) The circuit as recited in claim 1 wherein the sensor is CMOS NOR gate since the two-input CMOS NOR gate can be used as an enabling inverter with one input serving as an active low enable input and the other used as the logical input. ### Claim 7 (depends on 1) The circuit as recited in claim 1 wherein an odd number of CMOS sensing inverters control the gates of triggering NMOS transistors coupled to the PMOS transistor current mirror. ### Claim 8 (depends on 1) The circuit as recited in claim 1 wherein an odd number of CMOS sensing inverters control the gates of triggering PMOS transistors coupled to the NMOS transistor current mirror. ### Claim 9 (depends on 1) The circuit as recited in claim 1 wherein an even number of CMOS sensing inverters directly control the gate of NMOS transistor in current source if there are not additional NMOS transistor current mirror and N-bit triggering circuit array including triggering PMOS transistors which are coupled each other. ### Claim 10 (depends on 1) The circuit as recited in claim 1 wherein an even number of CMOS sensing inverters directly control the gate of PMOS transistor in current source if there are not additional PMOS current mirror and N-bit triggering circuit array including triggering NMOS transistors which are coupled each other. ### Claim 11 (depends on 1) The circuit as recited in claim 1 wherein capacitors are added to necessary nodes. ### Claim 12 (depends on 1) The circuit as recited in claim 1 wherein the current mirror is cascode current mirror. ### Claim 13 (depends on 1) The circuit as recited in claim 1 wherein the current mirror is the Wilson current mirror. ### Claim 14 (depends on 1) The circuit as recited in claim 1 wherein the current mirror is simple current mirror. ### Claim 15 (depends on 1) The circuit as recited in claim 1 wherein power-down inverter and power-down transistors are further added to turn off all transistors and CMOS gates so that no current flows into the circuit during power-down mode. ### Claim 16 (depends on 1) The circuit as recited in claim 1 wherein the output of the variable lock-in circuit is coupled to the output of a filter connected between the output and ground. ### Claim 17 (depends on 16) The circuit as recited in claim 16 wherein the output of the variable lock-in circuit is at ground to ensure that no current flows into the circuit when the power-down input is at the power supply. ### Claim 18 (depends on 1) The circuit as recited in claim 1 wherein the output of the variable lock-in circuit is coupled to the output of a filter connected between the output and power supply. ### Claim 19 (depends on 18) The circuit as recited in claim 18 wherein the output of the variable lock-in circuit is at power supply to ensure that no current flows into the circuit when the power-down input is at the power supply. ### Claim 20 (depends on 1) The circuit as recited in claim 1 wherein the variable lock-in circuit is applied to all phase-locked loops without regard to architectures, topologies, and schematics.