Circuit information generating apparatus and circuit information generating method

A circuit information generating method for generating circuit information incorporating therein a clock gating circuit, the method comprising:

• an obtaining step of obtaining functional structure information and execution sequence information from outside, the functional structure information defining a structure of a function and the execution sequence information defining an execution sequence of the function;
• a structure information generating step of generating, according to the execution sequence information and the functional structure information, circuit structure information in register transfer level which defines a plurality of circuits that execute the function according to the execution sequence;
• a gated clock information generating step of generating, according to the execution sequence information and the functional structure information, gated clock information in register transfer level which defines a clock control circuit that supplies, to each of at least one of the circuits, a gated clock that is set to halt clock input when the clock input is unnecessary;
• and
• an outputting step of outputting the gated clock information together with the circuit structure information.

A gated-clock combining method of combining gated clocks supplied to a plurality of circuits respectively, the method comprising:

• a retaining step of retaining a priority value table that indicates, for each of a plurality of circuits included in an operation processing circuit, a power reducing effect expected of gated clock supply to the circuit included in the operation processing circuit;
• a detecting step of, using the priority value table, detecting two gated clocks respectively to be supplied to two circuits exhibiting lowest power reducing effects of the circuits included in the operation processing circuit;
• a combining step of combining the detected two gated locks to generate a combined gated clock;
• and
• a supplying step of supplying the combined gated clock to the two circuits.

A circuit information generating program for generating circuit information incorporating therein a clock gating circuit, the program being fur executing:

• an obtaining step of obtaining functional structure information and execution sequence information from outside, the functional structure information
• defining a structure of a function and the execution sequence information defining an execution sequence of the function;
• a structure information generating step of generating, according to the execution sequence information and the functional structure information, circuit structure information in register transfer level which defines a plurality of circuits that execute the function according to the execution sequence;
• a gated clock information generating step of generating, according to the execution sequence information and the functional structure information, gated clock information in register transfer level which defines a clock control circuit that supplies, to each of at least one of the circuits, a gated clock that is set to halt clock input when the clock input is unnecessary;
• and
• an outputting step of outputting the gated clock information together with the circuit structure information.

A gated-clock combining program for combining gated clocks supplied to a plurality of circuit respectively, the program being for executing:

• a retaining step of retaining a priority value table that indicates, for each of a plurality of circuits included in an operation processing circuit, a power reducing effect expected of gated clock supply to the circuit included in the operation processing circuit;
• a detecting step of, using the priority value table, detecting two gated clocks respectively to be supplied to two circuits exhibiting lowest power reducing effects of the circuits included in the operation processing circuit;
• a combining step of combining the detected two gated clocks to generate a combined gated clock;
• and
• a supplying step of supplying the combined gated clock to the two circuits.