US 2006/0150133 A1 · Integrated circuit (IC) chip design method, program product and system

Abstract

A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.

Claims29

Dependent claims

A circuit design method comprising:

a) providing a circuit design for static timing analysis (STA);
b) selecting a gate from said circuit design;
c) determining initial performance characteristics for said selected gate;
d) determining a charge equivalent effective capacitance (CQeff) for said selected gate from determined said initial performance characteristics;
and
e) determining a gate delay for said selected gate using said CQeff as an effective load for said selected gate.

3 more elements

A computer program product for designing very large scale integrated (VLSI) circuits, said computer program product comprising a computer usable medium having computer readable program code thereon, said computer readable program code comprising:

computer readable program code means for receiving a circuit design for static timing analysis (STA);
computer readable program code means for providing technology parameters describing a technology for fabricating said circuit design;
computer readable program code means for selecting a gate from said circuit design;
computer readable program code means for determining initial performance characteristics for each said selected gate;
computer readable program code means for determining a charge equivalent effective capacitance (CQeff) for said selected gate responsive to said initial performance characteristics;
and
computer readable program code means for determining a gate delay for said selected gate responsive to a determined said CQeff.

4 more elements

A chip design system for designing very large scale integrated (VLSI) circuits and performing static timing analysis (STA) on VLSI circuit designs, said chip design system comprising:

input means for inputting a chip design and technology parameters describing a technology for fabricating said chip design;
storage means for storing gate look up tables for gates included in said chip design;
gate selection means for selecting a gate from said chip design;
gate performance determination means for determining initial performance characteristics for each said selected gate;
and
charge equivalent determination means for determining a charge equivalent effective capacitance (CQeff) for said selected gate responsive to said initial performance characteristics, a gate delay for said selected gate being determined by said gate performance determination means responsive to a determined said CQeff.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/274,556Filed 15 Nov 2005

Priority

17 Nov 2004

Published

6 Jul 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/3315
Design verification, e.g. functional simulation or model checking: using static timing analysis [STA]
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3312
Using simulation: timing analysis
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation

Integrated circuit (IC) chip design method, program product and system

Life of this patent

Integrated circuit (IC) chip design method, program product and system

Life of this patent

Abstract

Claims29