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AssigneeInternational Business Machines Corporation
InventorsKafai Lai, Chieh-Yu Lin, Nayak Jawahar, Mukherjee Maharaj
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A method is described for computing distance based and pattern density based design rules for the mask layout design of a VLSI chip so that the design satisfying the above design rules when manufactured on a wafer do not violate the specified tolerance on the critical dimensions (CD). The design rules are developed on the computed enclosed energy which is a convolution of the total optical energy and the pattern density of the mask. The total optical energy is the sum of the short range diffraction limited optical energy and the long range optical flare. The method steps for generating rules for a mask layout include: selecting a mask shape from a plurality thereof inputted from the mask layout, and determining a CD of the selected mask shape and a tolerance on variations of the CD; building a physical model of a component of the energy contributed by surrounding regions at a predetermined distance from the CD; using the physical model, computing the energy enclosed within the surrounding regions at the predetermined distance, and the maximum pattern density there of while remaining within the tolerance on variations of the CD; and outputting the maximum pattern density as a rule for the surrounding region at that distance.
A method for generating rules for a mask layout of a Very Large Scale Integrated Circuit (VLSI) chip comprising the steps of:
A method for generating rules for a mask layout of a Very Large Scale Integrated Circuit (VLSI) chip comprising the steps of:
A method for generating rules for a mask layout of a VLSI chip comprising the steps of:
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for generating rules for a mask layout of a VLSI chip, said method steps comprising:
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for generating rules for a mask layout of a VLSI chip, said method steps comprising:
Dependencies are inferred from the claim text.