Loading patent…
AssigneeInternational Business Machines Corporation
InventorsRobert Allen, Michael Gray, Jason Hibbeler, Mervyn Tan, Robert Walker
Estimating the term…
A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.
A method of calculating critical area in an integrated circuit design, said method comprising:
A method of optimizing critical area in an integrated circuit design, said method comprising:
A method of optimizing critical area in an integrated circuit design, said method comprising:
The method in claim 15, wherein said process of associating said cost functions comprises mapping points in said spacing between said edges in said integrated circuit design up to when the size of defects located at said points triggers an electrical fault between said edges in said integrated circuit design, wherein said mapping forms Voronoi cells.
The method in claim 16, wherein said process of associating said cost functions further comprises using a normal vector representing said Voronoi cells defined in terms of said variables.
The method in claim 15, wherein said process of associating said cost functions further comprises identifying Voronoi bisectors where Voronoi cells meet.
The method in claim 18, wherein said Voronoi bisectors are defined by vertices at the ends of said Voronoi bisectors;
The method in claim 19, wherein said cost function calculates critical area contributions of said Voronoi bisectors as said variables change as the layout of said integrated circuit design changes.
A service for calculating critical area in an integrated circuit design, said service comprising:
The service in claim 22, wherein said process of associating said cost functions comprises mapping points in said spacing between said edges in said integrated circuit design up to when the size of defects located at said points triggers an electrical fault between said edges in said integrated circuit design, wherein said mapping forms Voronoi cells.
The service in claim 23, wherein said process of associating said cost functions further comprises using a normal vector representing said Voronoi cells defined in terms of said variables.
The service in claim 22, wherein said process of associating said cost functions further comprises identifying Voronoi bisectors where Voronoi cells meet.
The service in claim 25, wherein said Voronoi bisectors are defined by vertices at the ends of said Voronoi bisectors;
The service in claim 26, wherein said cost function calculates critical area contributions of said Voronoi bisectors as said variables change as the layout of said integrated circuit design changes.
A program storage device readable by computer, tangibly embodied a program of instructions executable by said computer for performing a method of calculating critical area in an integrated circuit design, said method comprising:
The program storage device in claim 29, wherein said process of associating said cost functions comprises mapping points in said spacing between said edges in said integrated circuit design up to when the size of defects located at said points triggers an electrical fault between said edges in said integrated circuit design, wherein said mapping forms Voronoi cells.
The program storage device in claim 30, wherein said process of associating said cost functions further comprises using a normal vector representing said Voronoi cells defined in terms of said variables.
The program storage device in claim 29, wherein said process of associating said cost functions further comprises identifying Voronoi bisectors where Voronoi cells meet.
The program storage device in claim 32, wherein said Voronoi bisectors are defined by vertices at the ends of said Voronoi bisectors;
The program storage device in claim 33, wherein said cost function calculates critical area contributions of said Voronoi bisectors as said variables change as the layout of said integrated circuit design changes.
A system for calculating critical area in an integrated circuit design, said system comprising:
A method of optimizing critical area in an integrated circuit design, said method comprising:
The method in claim 37, wherein said process of associating said cost functions comprises mapping points in said spacing between said edges in said integrated circuit design up to when the size of defects located at said points triggers an electrical fault between said edges in said integrated circuit design, wherein said mapping forms Voronoi cells.
The method in claim 38, wherein said process of associating said cost functions further comprises using a normal vector representing said Voronoi cells defined in terms of said variables.
The method in claim 37, wherein said process of associating said cost functions further comprises identifying Voronoi bisectors where Voronoi cells meet.
The method in claim 40, wherein said Voronoi bisectors are defined by vertices at the ends of said Voronoi bisectors;
The method in claim 41, wherein said cost function calculates critical area contributions of said Voronoi bisectors as said variables change as the layout of said integrated circuit design changes.
Dependencies are inferred from the claim text.