US 2006/0150127 A1 · Method of achieving timing closure in digital integrated circuits by optimizing individual macros

Abstract

Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

Claims13

Dependent claims

A method of achieving timing convergence of one of a digital integrated circuit and functional unit of a digital integrated circuit comprising of the steps of:

partitioning the design into macros;
apportioning a timing and area budget to each of said macros;
creating an objective function fo rthe optimization of at least one of said macros having contributions from a plurality of primary output signals in said macro;
improving the timing chracteristics of each of the at least one selected macros by attempting to minimize said objective function;
timing the overall design;
and
re-apportioning the timing and area budgets and repeating the said improving and timing steps until the required specifications are met.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/296,780Filed 7 Dec 2005

Priority

12 May 2003

Published

6 Jul 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3312
Using simulation: timing analysis
G06F 30/3315
Design verification, e.g. functional simulation or model checking: using static timing analysis [STA]
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation

Method of achieving timing closure in digital integrated circuits by optimizing individual macros

Life of this patent

Method of achieving timing closure in digital integrated circuits by optimizing individual macros

Life of this patent

Abstract

Claims13