Track buffer in a parallel decoder
AssigneeFreescale Semiconductor, Inc.
InventorsBo Wang, Adrian Macias
Life of this patent
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Abstract
A method (700) and apparatus (600) are described for performing 2M-1 parallel ACS operations to generate 2M path metric outputs and buffering the 2M path metric outputs in connection with a track buffer (112) in an Ultrawide Bandwidth (UWB) receiver for decoding a message sequence encoded according to a convolutional code. Contents of the track buffer are updated in accordance with Register Exchange and outputs from the track buffer can further be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.
Claims16
An integrated circuit capable of conducting a decoding operation on a received sequence of k symbols associated with an Ultra Wide Band (UWB) transmission, the received sequence presumed to include an encoded representation of a message sequence of n symbols encoded according to a convolutional code of rate n/k having a constraint K and having 2M code states, where M is equal to K-1, the received sequence received according to a symbol rate associated with the message sequence, the integrated circuit comprising:
- 2M-1 parallel Add Compare Select (ACS) elements associated with the 2M code states configured to generate 2M path metric outputs;
- and
- a track buffer including 2M path registers configured to be capable of storing the 2M path metric outputs from the 2M-1 parallel Add Compare Select (ACS) elements.
A method for decoding a received sequence of k symbols associated with an Ultra Wide Band (UWB) transmission, the received sequence presumed to include an encoded representation of a message sequence of n symbols encoded according to a convolutional code of rate n/k having a constraint K and having 2M code states, where M is equal to K-1, the sequence received according to a symbol rate, the method comprising:
- performing, substantially in parallel, 2M-1 Add Compare Select (ACS) operations associated with the 2M code states and generating 2M path metric outputs;
- and
- storing the 2M path metric outputs in 2M corresponding path registers.
An apparatus configured to be capable of conducting a decoding operation on received sequence of k symbols associated with an Ultra Wide Band (UWB) transmission, the received sequence presumed to include an encoded representation of a message sequence of n symbols encoded according to a convolutional code of rate n/k, the convolutional code having a constraint K and having 2M code states, where M=K-1, the apparatus comprising:
- a memory, and
- a processor coupled to the memory, the processor configured to:
- input the received sequence according to a symbol rate associated with the message sequence;
- perform, substantially in parallel, 2M-1 Add Compare Select (ACS) operations associated with the 2M code states to generate 2M path metric outputs;
- and
- store the 2M path metric outputs generated from the 2M ACS operations in the memory.
Dependencies are inferred from the claim text.