Method for clock synchronization validation in integrated circuit design
AssigneeAtrenta, Inc.
InventorsMohamed SARWARY, Mohammad MOVAHED EZAZI, Bernard MURPHY
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Abstract
Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.
Claims27
A method for verifying unstable clock-domain crossings in integrated circuit (IC) designs, comprising:
- identifying candidate unstable clock-domain crossings using clock synchronization analysis tool;
- performing a validity check for the candidate clock-domain crossing;
- and
- eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable crossing.
A computer program product, including a computer readable medium with computer instructions, for use by a computer to perform operations for verifying unstable clock-domain crossings in integrated circuit (IC) designs, comprising:
- identifying candidate unstable clock-domain crossings using clock synchronization analysis tool;
- performing a validity check for the candidate clock-domain crossing;
- and
- eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable crossing.
A computer system, adapted to implement a method for detecting unstable clock-domain crossings in a design of an integrated circuit (IC), comprising:
- a processor;
- and
- a memory including software instructions adapted to enable the computer system to perform the operations of:
- identifying candidate unstable clock-domain crossings using clock synchronization analysis tool;
- performing a validity check for the candidate clock-domain crossing;
- and
- eliminating a candidate unstable clock-domain crossing when the validity check does not indicate an unstable crossing.
Dependencies are inferred from the claim text.