Method and system for resetting fault tolerant computer system

A system for resetting a fault tolerant computer equipped with a plurality of modules, comprising:

• means for generating a reset requesting signal by one of the modules;
• means for dividing the reset requesting signal to first and second reset requesting signals;
• means for transmitting the second reset requesting signal to the other module;
• means for delaying the first reset requesting signal in the module by a time required for transmitting the second reset requesting signal to the other module;
• means for resetting at least one CPU included in the one module by a first CPU reset signal generated based on the first reset requesting signal delayed in the one module;
• and
• means for resetting at least one CPU included in the other module by a second CPU reset signal generated based on the second reset requesting signal transmitted to the other module.

A fault tolerant controller used for a fault tolerant computer equipped with a plurality of modules, comprising:

• reset requesting signal generation means for generating a reset requesting signal;
• dividing means for dividing the reset requesting signal to first and second reset requesting signals;
• transmission means for transmitting the second reset requesting signal to a fault tolerant controller included in a module other than a module which includes the controller;
• first delaying means for delaying the first reset requesting signal by a time required for transmitting the second reset requesting signal to the fault tolerant controller included in the module other than the module which includes the controller;
• and
• CPU resetting means for resetting at least one CPU included in the module which includes the controller by a first CPU reset signal generated based on the delayed first reset requesting signal.