Debugging apparatus

A debugging apparatus for transmitting and receiving debug data between a host computer connected to a system LSI comprising a plurality of CPUs and a plurality of storage means connected to the CPUs and the selected CPU to be debugged from among the CPUs, said debugging apparatus comprising:

• source address storage means for storing a source address of the CPU to be debugged set by the host computer, source CPU identifier storage means for storing the CPU identifier of the CPU to be debugged whose source address is set, destination address storage means for storing a destination address of the CPU to be debugged set by the host computer, destination CPU identifier storage means for storing the CPU identifier of the CPU to be debugged whose destination address is set, and debug data transfer means for transferring data between the host computer and the storage means connected to the CPU to be debugged indicated by the CPU identifier in accordance with the source address and the source CPU identifier or the destination address and the destination CPU identifier.

A debugging apparatus for transmitting and receiving debug data to and from a host computer connected to a system LSI comprising a plurality of CPUs and a plurality of storage means connected to the CPUs, said debugging apparatus comprising:

• debug object selection means being capable of selecting the CPU to be debugged from among the CPUs in accordance with a debug object selection request transmitted from the host computer and stopping any other CPU not to be debugged than the CPU to be debugged, source address storage means for storing a source address of the CPU to be debugged set by the host computer, destination address storage means for storing a destination address of the CPU to be debugged set by the host computer, and debug data transfer means for transferring data between the host computer and the storage means connected to the CPU to be debugged in accordance with the source address or the destination address.