Duplex fault tolerant system and method using DMA
AssigneeLG-Nortel Co., Ltd.
InventorCheol Ju
Life of this patent
Estimating the term…
Abstract
A duplex fault tolerant system and method uses a direct memory access (DMA) scheme to mirror the storage of data in the memories of active and standby circuits. The active circuit includes a monitoring unit to detect a write operation on a system bus, a DMA trigger circuit to generate a trigger signal in response to detection of the write operation, and a FIFO unit to store an address in an active-side memory of where data associated with the write operation is stored. A DMA transfer unit then transfers the data and address to the standby circuit in response to the trigger signal.
Claims26
A duplex fault tolerant system, comprising:
- a monitoring circuit which detects a write operation on a bus;
- a DMA trigger circuit which receives a detection signal from the monitoring circuit indicative of the write operation;
- and
- a storage circuit which stores information indicative of an address in an active-side memory where data associated with the write operation is stored,
- wherein the DMA trigger circuit sends a trigger signal to a DMA unit containing said address information and wherein the DMA unit transfers a copy of the data and the address information to a standby circuit.
A duplex fault tolerant system, comprising:
- an active-side circuit including a memory and a system controller coupled to a bus, wherein the system controller receives information indicative of an address where data is stored in the memory and sends a copy of the data and the address information to a standby-side circuit through a DMA unit.
A duplex fault tolerant system, comprising:
- a duplex logic circuit to detect a write operation on a bus and to store data associated with the write operation in a first memory;
- a FIFO circuit to store an address of the data in the first memory;
- and
- a DMA circuit to transfer a copy of the data stored in the first memory and the address stored in the FIFO circuit to a second memory.
A duplex fault tolerant method, comprising:
- capturing an address from a write operation detected on a bus;
- storing said address in a buffer;
- generating a trigger signal containing said address;
- and
- sending said address stored in the buffer and data stored in an active-side memory at said address to a standby circuit in response to the trigger signal, said data and address sent to the standby circuit through a DMA unit.
Dependencies are inferred from the claim text.