Fault tolerant computer system and interrupt control method for the same

An interrupt control method comprising:

• providing a fault tolerant computer system including a primary system and a secondary system,
• wherein said primary system comprises a first CPU, a first FT control section connected with said first CPU, a first south bridge connected electrically and operatively with said first FT control section, a first PCI bridge connected with said first FT control section, and a first I/O device group connected with said first PCI bridge,
• said secondary system comprises a second CPU, a second FT control section connected with said second CPU, a second south bridge connected electrically and not connected operatively with said second FT control section, a second PCI bridge connected with said second FT control section, and a second I/O device group connected with said second PCI bridge,
• said first FT control section and said second FT control section are connected by a link section, and
• said first FT control section has a first master IOAPIC control section and said second FT control section has a second master IOAPIC control section;
• transferring a first interrupt request issued from one of I/O devices of said first I/O device group to said first master IOAPIC control section in a legacy mode, in which an operating system does not yet operate, when said primary system is set as an active system and said secondary system is set as an standby system and operates in synchronization with said primary system;
• forwarding said first interrupt request to said second master IOAPIC control section of said second FT control section through said link section;
• transferring said first interrupt request to said first CPU from said first master IOAPIC control section by transferring said first interrupt request to said first master IOAPIC control section through said PIC control section of said first south bridge;
• and
• transferring said first interrupt request to said second CPU from said second master IOAPIC control section by transferring said first interrupt request to said second master IOAPIC control section through said PIC control section of said second south bridge.