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US 2006/0149988 A1Published application
Calculating apparatus having a plurality of stages
OwnerTerence Thomas, Stephen Davisinventors
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Abstract
A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.
Claims15
A method for processing data comprising:
- providing a pipeline processor including a plurality of processing elements arranged in a serial array, each processing element having a forward processing path and a reverse path;
- providing a clock signal to each of the plurality of processing elements in the serial array such that the clock signal arrives at each processing element beyond the first processing element delayed relative to the clock signal arrives at each processing element beyond the first processing element delayed relative to the clock signal arriving at a preceding processing element, the clock signal provided to one of the plurality of processing elements being delayed relative to the clock signal provided to another one of the plurality of processing elements by a finite period of time that is a fraction of a clock period;
- providing data to the first processing element for processing therein;
- and
- propagating the data to at least a next processing element for additional processing therein.
2 more elements
A method for processing data within a pipeline processor comprising:
- providing a clock signal in a first direction along a first portion of the pipeline processor having a plurality of processing elements such that the clock signal arrives at each of the processing elements beyond the first processing element of the first portion delayed relative to the clock signal arriving at a preceding processing element of the same first portion;
- providing a clock signal in a second substantially opposite direction along a second other portion of the pipeline processor having a same number of processing elements as the first portion such that the clock signal arrives at each of the processing elements beyond the first processing element of the second other portion delayed relative to the clock signal arriving at a preceding processing element of the same second other portion;
- providing data to the first processing element of the first portion of the pipeline processor for processing therein,
- the delay to the last processing element of the first portion being an approximately same delay as the delay to the last processing element of the second portion, at center of the pipeline processor the two adjacent processing elements being in synchronization.
1 more element
Dependencies are inferred from the claim text.