Semiconductor device with clock failure detection circuitry

A semiconductor device comprising:

• an oscillator circuit developing a clock;
• a CPU;
• a first counter counting clock pulses of said clock during a first period to obtain a first count value;
• a second counter counting clock pulses of said clock during a second period following said first period to obtain a second count value;
• a third counter counting clock pulses of said clock during a third period following said second period to obtain a third count value;
• and
• a failure detector circuit developing an oscillation failure detect signal;
• wherein said first counter activates a first detect signal at said second period when said first count value is out of a predetermined count value range, and resets said first count value at said third period,
• wherein said second counter activates a second detect signal at said third period when said second count value is out of said predetermined count value range, and resets said second count value at a fourth period following said third period,
• wherein said third counter activates a third detect signal at said fourth period when said third count value is out of said predetermined count value range, and resets said third count value at a fifth period following said fourth period,
• wherein said failure detector circuit activates said oscillation failure detect signal in response to said first to third detect signals being activated, and
• wherein said CPU stops operation in response to said oscillation failure detect signal being activated.