Memory power saving state
AssigneeIntel Corporation
InventorPete Vogt
Life of this patent
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Abstract
Embodiments described herein provide a power saving state for a memory system. For example, a memory system may derive clocking information from a training pattern sent over a memory channel. A memory may comprise a link to receive training frames, and circuitry to derive a clock from the training frames, and place the memory module in a low power state between training frames. Embodiments as described herein may utilize periodic training frames to implement a power saving state on the channel or the memory system, either in whole or in part.
Claims18
A memory module comprising:
- a link to receive training frames;
- and
- circuitry to derive a clock from the training frames, and place the memory module in a low power state between training frames.
A mobile computing system comprising:
- a display;
- a memory module including a link to receive training frames;
- and
- circuitry to derive a clock from the training frames and place the memory module in a low power state.
A method comprising:
- receiving a training frame at a memory module from a memory channel, to allow derivation of a clock;
- sending a signal from a memory controller to a memory module, the signal designating entry to a low power state;
- and
- powering down the memory channel in response to the signal.
A machine-readable medium containing instructions that, when executed, cause a machine to:
- receive a training frame at a memory module from a memory channel to allow derivation of a clock;
- send a signal from a memory controller to a memory module, the signal designating entry to a low power state;
- and
- power down the memory channel in response to the signal.
Dependencies are inferred from the claim text.