Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions

A method of reducing power consumption is a processor, comprising:

• detecting that the target address of a PC-relative or absolute address branch instruction is in the same memory page as the branch instruction address;
• storing an indicator of said detection;
• suppressing a TLB access when fetching said target address during a first execution of said branch instruction, in response to said indicator;
• and
• suppressing a TLB access when fetching said target address during a second execution of said branch instruction, in response to said indicator.

A processor, comprising:

• page residence detection logic generating an indication that the target address of a PC-relative or absolute address branch instruction is in the same memory page as the branch instruction address;
• memory storing said indication;
• and
• a TLB generating memory access permission information upon instruction fetches, said TLB suppressed in response to said indication in fetching an instruction at said target address while executing said branch instruction.

A processor, comprising:

• a memory interface accessing memory external to said processor, said memory organized as logical pages;
• a cache memory in data transfer relationship with said memory interface, said cache memory storing instructions;
• and
• a pre-decoder interposed between said memory interface and said cache memory, said pre-decoder calculating the branch target address of a PC-relative or absolute address branch instruction prior to storing said instruction in said cache memory.