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US 2006/0149952 A1Published application
Exception handling in a multiprocessor system
AssigneeInternational Business Machines Corporation
InventorsStephen Blinick, Ricardo Padilla
Life of this patent
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Abstract
In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed to a data structure which provides a programmable exception vector to additional exception handler code. This additional code may be executed as if it were located at the architecture-defined exception vector. Other embodiments are described and claimed.
Claims32
A method of code execution in a system having first and second processors, comprising:
- said first processor encountering a first exception;
- said first processor jumping to execute a first exception handler code at a first predetermined address;
- said first processor executing said first exception handler code at said first predetermined address, wherein said first instruction handler code directs said first processor to read a value at a first data structure;
- said first processor jumping to execute a second exception handler code at a second address as a function of the value read from said first data structure;
- and
- said first processor executing said second exception handler code to handle said first exception.
3 more elements
A system, comprising:
- a first processor having a first data structure adapted to store a value;
- a second processor;
- a memory adapted to store a first exception handler code at a first predetermined address and a second exception handler code at a second address;
- said first processor having logic adapted to:
- encounter a first exception;
- jump to execute said first exception handler code at said first predetermined address;
- execute said first exception handler code at said first predetermined address, wherein said first instruction handler code directs said first processor to read a value at a first data structure;
- jump to execute said second exception handler code at said second address as a function of the value read from said first data structure;
- and
- execute said second exception handler code to handle said first exception.
7 more elements
An article of manufacture comprising:
- code enabled to be executed by a system to perform operations, wherein the system has a first processor having a first data structure adapted to store a value, a second processor, and a memory adapted to store a first exception handler code at a first predetermined address and a second exception handler code at a second address, wherein the operations comprise:
- said first processor encountering a first exception;
- said first processor jumping to execute said first exception handler code at said first predetermined address;
- said first processor executing said first exception handler code at said first predetermined address, wherein said first instruction handler code directs said first processor to read a value at a first data structure;
- said first processor jumping to execute said second exception handler code at said second address as a function of the value read from said first data structure;
- and
- said first processor executing said second exception handler code to handle said first exception.
4 more elements
A method for deploying computing instructions, comprising:
- integrating computer-readable code into a system, wherein the system has a first processor having a first data structure adapted to store a value, a second processor, and a memory adapted to store a first exception handler code at a first predetermined address and a second exception handler code at a second address, and wherein the code in combination with the system is enabled to cause the system to perform:
- said first processor encountering a first exception;
- said first processor jumping to execute said first exception handler code at said first predetermined address;
- said first processor executing said first exception handler code at said first predetermined address, wherein said first instruction handler code directs said first processor to read a value at a first data structure;
- said first processor jumping to execute said second exception handler code at said second address as a function of the value read from said first data structure;
- and
- said first processor executing said second exception handler code to handle said first exception.
4 more elements
Dependencies are inferred from the claim text.