Method and apparatus for vector execution on a scalar machine

A method of operating a processor to execute a sequence of instructions, the method comprising:

• a) executing instructions in a first mode, comprising:
• i) fetching a first instruction;
• ii) fetching operand for the first instruction;
• iii) executing the first instruction with the operands;
• iv) fetching a second instruction before subsequently executing the first instruction;
• and
• b) executing instructions in a second mode, comprising:
• i) fetching a third instruction;
• ii) fetching operand for the third instruction;
• iii) executing the third instruction with the fetched operand;
• iv) fetching a second operand for the third instruction;
• v) executing the third instruction with the second operand before executing another instruction.

A processor comprising:

• a) an instruction decode circuit having an address output;
• b) a rename circuit having an address input coupled to the address output of the instruction decode circuit and an address output, the rename circuit comprising:
• i) a counter;
• ii) an arithmetic circuit having a first input coupled to the address input and a second input coupled to the counter and a renamed output, the arithmetic circuit configured to provide at the renamed output a value representing a value at the first input offset by an amount proportional to a value at the second input;
• iii) a switching circuit having a first input coupled to the address input, a second input coupled to the renamed output of the arithmetic circuit, a control input and an output coupled to the address output of the rename circuit, the switching circuit configured to couple a value at the first input of the switching circuit or a value at the second input of the switching circuit to the output selectively in response to a value of the control input;
• and
• c) a data access circuit, having an address input coupled to the address output of the rename circuit.