Implementation to save and restore processor registers on a context switch
AssigneeIntel Corporation
InventorShubhendu Mukherjee
Life of this patent
Estimating the term…
Abstract
A method and apparatus for enabling a processor to perform a save and restore on a context switch incrementally and on demand. In one embodiment, when OS switches to a new process, the processor saves only those registers that have been modified in the current process. The processor may not bring in these registers for the new process, rather, the processor will load them on demand. If instructions from the new process do not locate their source operand in the register file, it will initiate a miss handling flow for the register and restore the register value in the register file. Then the pipeline will reissue the instruction that missed in the register file.
Claims23
A processor comprising:
- a first set of registers allocated to a first process;
- a circuit to selectively store contents of a first subset of the first set of registers to a memory upon making current a second process, wherein the stored contents of the first subset of the first set of registers are modified registers during the first process.
A method comprising:
- allocating a first set of registers for a first process;
- storing content of a first subset of the first set of registers;
- switching to a second process;
- requesting the content of the first subset of the first set of registers by the second process;
- and
- reading content of the first subset of the first set of registers upon request by the second process.
A system comprising:
- A processor including a first set of registers allocated to a first process, and a circuit to selectively store contents of a first subset of the first set of registers to a memory upon making current a second process, wherein the stored contents of the first subset of the first set of registers are modified registers during the first process;
- an interconnect to couple the processor to input/output devices;
- and
- an audio input/output device coupled to the interconnect and to the processor.
Dependencies are inferred from the claim text.