Multimedia coprocessor control mechanism including alignment or broadcast instructions
AssigneeMarvell International Ltd.
InventorsNigel Paver, Wing Yu, Murli Ganeshan
Life of this patent
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Abstract
A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.
Claims22
A method comprising:
- performing data processing using a main processor in response to a stream of data processing instructions, said data processing instructions including at least one coprocessor instruction;
- providing two source registers and a destination register for said at least one coprocessor instruction;
- providing a coprocessor instruction that includes an opcode specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instruction;
- and
- executing an instruction to extract values from said source registers and to place the values in said destination register, said instruction including information from which to determine the offset of the values to enable those values to be extracted from said source registers.
An article comprising a medium storing instructions that, if executed, enable a processor-based system to:
- perform data processing using a main processor in response to a stream of data processing instructions, said data processing instructions including at least one coprocessor instruction;
- provide two source registers and one destination register for said at least one coprocessor instruction;
- provide a coprocessor instruction that includes an opcode specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instruction;
- and
- execute an instruction to extract values from said source registers and to place the values in said destination register, said instruction including information from which to determine the offset of the values to enable those values to be extracted from said source registers.
A coprocessor comprising:
- a main processor including an arithmetic flag;
- and
- a storage storing opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instructions, said coprocessor to execute an instruction to extract values from said source registers and to place the values in said destination register, said instruction including information from which to determine the offset of the values to enable those values to be extracted from said source registers.
A system comprising:
- a main processor;
- a coprocessor coupled to said main processor, said coprocessor including opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instructions, said coprocessor to allocate two source registers and one destination register for a coprocessor instruction, said coprocessor including an instruction to extract values from said source registers and to place those values in said destination register, said instruction including information from which to determine the offset of the values to enable said values to be extracted from said source registers;
- and
- a wireless interface coupled to said main processor.
Dependencies are inferred from the claim text.