Load lookahead prefetch for microprocessors

A data processing system provides for speculative execution of instructions by a microprocessor non speculative execution of instructions and commits results of said non speculative instructions to at least one architected facility, comprising:

• means for determining the occurrence of a stall condition during the execution of said non speculative instructions;
• means for speculatively executing instructions during said stall condition;
• means for determining the validity of data utilized during said speculative execution;
• and
• means for retrieving valid data for use by said non speculative instructions upon removal of said stall condition.

A computer program product resident on a computer readable media that controls speculative execution of instructions in a microprocessor that executes non-speculative instructions and commits results of said non speculative instructions to at least one architected facility, said computer program product, comprising:

• means for determining the occurrence of a stall condition during the execution of said non speculative instructions;
• means for speculatively executing instructions during said stall condition;
• means for determining validity of data utilized during said speculative execution;
• and
• means for retrieving valid data for use by said non speculative instructions upon removal of said stall condition.

A data processing apparatus that provides for speculative execution of instructions by a microprocessor, which executes non speculative instructions and commits results of said non speculative instructions to at least one architected facility, comprising:

• logic that detects the occurrence of a stall condition wherein at least one of said non speculative instructions is unable to be processed;
• at least one functional unit in said microprocessor that executes at least one of said speculative instructions during said stall condition;
• circuitry that determines validity of data utilized during said speculative execution;
• and
• a memory hierarchy that transfers valid data to a cache proximate said microprocessor, said valid data for use by said non speculative instructions upon removal of said stall condition and continuance of non-speculative execution of said instructions.

A data processing apparatus that provides for speculative execution of instructions by a microprocessor, which executes non speculative instructions and commits results of said non speculative instructions to at least one architected facility, comprising:

• logic that detects the occurrence of a stall condition wherein at least one of said non speculative instructions is unable to be processed;
• at least one functional unit in said microprocessor that executes speculative instructions, including at least one load instruction, across multiple pipeline stages during said stall condition;
• logic that determines validity of data utilized during said speculative execution;
• a memory hierarchy that transfers valid data to a cache proximate said microprocessor, said valid data for use by said non speculative instructions upon removal of said stall condition and continuance of non speculative execution of said instructions;
• a dirty bit field in said instructions that tracks the validity of said data associated with the speculatively executed instructions during their execution in said multiple pipeline stages of said microprocessor, said dirty bit field having a dirty bit which is provided to said speculative executing instructions which have a dependency on said data, said bit indicating a valid state of said data;
• and
• a dependency on load bit field in said instructions that monitors a dependency of said speculatively executed instructions relative to one another during their execution in said multiple pipeline stages of said microprocessor, said dependency on load bit field having at least one dependency on load bit that determines at which one of said multiple pipeline stages said data retrieved by said load instruction is determined to be valid or invalid;
• and
• wherein said load instruction moves said valid data within said memory hierarchy by retrieving the valid data from main memory and storing said valid data in said cache such that said non speculative instructions will have relatively lower latency to said valid data upon removal of said stall condition.