Branch lookahead prefetch for microprocessors

Abstract

A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. In particular, the method can detect a load instruction miss which results in the stall condition. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid. The speculative execution of instructions can occur across multiple pipeline stages of the microprocessor, and the validity of the data is tracked during their execution in the multiple pipeline stages while monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages. A branch prediction unit predicts a path of the branch instruction prior to detection of the stall condition, and fetches speculative instructions from the predicted path into an instruction queue. If the speculative execution of the branch instruction indicates it was mispredicted, the speculative instructions are flushed from the pipeline and instruction queue, and the branch prediction information is updated based on results of the speculative execution of the branch instruction. The speculative execution of the instructions occurs without altering any architected facilities of the microprocessor.

Dependencies are inferred from the claim text.