Data processing circuit, multiplier unit with pipeline, ALU and shift register unit for use in a data processing circuit

A processor comprising:

• a multiplier unit adjustable to multiply integer data words of any of a plurality of different lengths in response to instructions defined in an instruction set of the processor, the plurality of different lengths being integer multiples of each other, wherein the instruction set has a hierarchy of instruction levels, each of which can be used by a programmer to define instructions for the processor;
• an arithmetic logic unit (ALU) adjustable to perform arithmetic operations on integer data words of any of the plurality of different lengths in response to instructions defined in the instruction set;
• a shift register to perform shift operations in response to instructions defined in the instruction set;
• a plurality of dedicated output buses, one for each of the multiplier unit, the ALU, and the shift register;
• and
• a plurality of bus registers, each coupled to an output of a separate corresponding one of the multiplier unit, the ALU, and the shift register and to a separate corresponding one of the plurality of dedicated output buses, the bus registers to hold outputs of the multiplier unit, the ALU, and the shift register, respectively,
• wherein the outputs of the multiplier unit, the ALU, and the shift register can be explicitly referenced by instructions defined from the instruction set.