Aligning instructions using a variable width instruction alignment engine
AssigneesIntel Corporation, a Delaware corporation, Analog Devices Inc., a Massachusetts corporation
InventorsThomas Tomazin, William Anderson, Charles Roth, Kayla Chalmers, Juan Revilla, Ravi Singh
Life of this patent
Estimating the term…
Abstract
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
Claims21
1-3. (canceled)
The method of claim 25, further comprising storing a first instruction across a plurality of sub-buffers prior to processing the instructions.
The method of claim 25, further comprising adding the size of the first instruction to a current instruction position to determine the beginning of the second instruction.
The method of claim 25, further comprising:
- aligning ahead a number of cycles at least equal to a cache latency with determining whether processing the second instruction will deplete at least one of said plurality of buffers occurring at least said number of cycles before instructing the plurality of buffers to receive additional instructions.
The method of claim 25, wherein the instructions are aligned in a digital signal processor.
The method of claim 25, further comprising:
- issuing a request to a memory to reload the plurality of buffers.
9-18. (canceled)
The processor of claim 33, wherein the processor aligns ahead a number of cycles at least equal to a cache latency with predicting when at least one of the plurality of buffers will be empty occurring at least said number of cycles before sending a signal to instruct said at least one of the plurality of buffers to load additional instruction data.
The processor of claim 33, wherein the processor is a digital signal processor.
21-23. (canceled)
The apparatus of claim 27, wherein a first instruction is stored across a plurality of sub-buffers prior to processing the instructions.
A method of aligning instructions in a processor comprising:
- storing a plurality of instructions of different widths in a plurality of buffers, each buffer including a plurality of sub-buffers, each sub-buffer storing a unit instruction width, with an instruction of greater than a unit instruction width stored in more than one sub-buffer;
- aligning a first instruction from the buffers;
- decoding a width of the first instruction;
- selecting at least one of the plurality of sub-buffers from which to output the first instruction;
- determining a beginning of a second instruction from selected ones of the plurality of sub-buffers based on the size of the first instruction, decoding the size of the second instruction, and determining whether processing of the second instruction will deplete at least one of the plurality of buffers based on determining whether the second instruction occupies sub-buffers that include a transition between two of the buffer;
- and
- based on determining whether processing the second instruction will deplete at least one of said plurality of buffer, receiving additional instructions in the plurality of buffers.
An apparatus, including instructions residing on a machine-readable storage medium, for use in a machine system to align instructions in a processor, the instructions causing the machine to:
- store a plurality of instructions of different widths in a plurality of buffers, each buffer including a plurality of sub-buffers, each sub-buffer storing a unit instruction width, with an instruction of greater than a unit instruction width stored in more than one sub-buffer;
- decode a width of a first instruction from said plurality of buffers;
- select at least one of said plurality of sub-buffers from which to output the first instruction;
- determine a beginning of a second instruction from selected ones of the plurality of sub-buffers based on the determined width of the first instruction, decode the width of the second instruction, and determine whether processing of the second instruction will deplete at least one of the plurality of buffers based on determining whether the second instruction occupies sub-buffers that include a transition between two of the buffers;
- and
- based on the instructions to determine whether processing the second instruction will deplete at least one of the plurality of buffers,
- instruct the plurality of buffers to receive additional instructions if the processing of the second instruction will deplete at least one of the plurality of buffers.
A method of processing instructions within a processor, comprising:
- storing instructions of different widths within a cache having a plurality of buffers, each buffer having a plurality of subportions, each subportion in the cache storing a unit instruction width, where an instruction of unit width takes up a single subportion in the cache, and an instruction of more than said unit width takes up more than one subportion within the cache;
- multiplexing each of the subportions of the cache to an output of the cache, and selecting contents of at least one of said cache subportions as a current instruction;
- during said selecting said current instruction,
- predicting which of said buffers within said cache will be depleted of instruction data based on determining whether an instruction occupies subportions that include a transition between two of the buffers;
- and
- instructing loading of the buffers that are predicted to be depleted with additional instruction data.
A processor comprising:
- a plurality of buffers, each buffer including a plurality of sub-buffers a to store a plurality of instructions of different widths, each of the sub-buffers storing a unit instruction width, and with instructions of greater than a unit instruction width stored in multiple one of the sub-buffers;
- a multiplexer, coupled to the plurality of sub-buffers, and to select and align contents of at least one of said plurality of sub-buffers from any of the sub-buffers within said buffers as a current instruction;
- and
- a predictor, to predict when at least one of the plurality of buffers will be empty based on determining whether an instruction occupies sub-buffers that include a transition between two of the buffers, and to send a signal to instruct the at least one of the plurality of buffers to load additional instruction data.
Dependencies are inferred from the claim text.