Processor capable of multi-threaded execution of a plurality of instruction-sets

Abstract

A processor (100) capable of receiving a plurality of instructions sets from at least one memory (50), and capable of multi-threaded execution of the plurality of instruction sets. The processor includes at least one decoder (130) capable of decoding and interpreting instructions from the plurality of instruction sets. The processor also includes at least one mode indicator (140) capable of determining the active instruction-set mode, and changes modes of a software or hardware command and at least one execution unit (110) for concurrent processing of multiple threads, such that each thread can be from a different instruction set, and such that the processor processes the instructions according to the active instruction-set, which is determined by the mode indicator (140), and by allowing concurrent execution of several threads of several instruction sets.

Dependencies are inferred from the claim text.