# US 2006/0149926 A1 · Control words for instruction packets of processors and methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2006/0149926 A1 - Document ID: US20060149926A1 - Status: Published application - Kind: A1 - Application number: 11/019,281 - Filed: 2004-12-23 - Published: 2006-07-06 - Earliest claimed: 2004-12-23 - Inventors: Yuval Sapir; Eran Briman; Roy Glasner - Web page: https://patentgrep.com/patent/US20060149926A1 ## CPC - G06F 8/4434: {Reducing the memory space required by the program code} - G06F 9/3828: {with global bypass, e.g. between pipelines, between clusters} - G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Control words are included in instruction packets to influence how one or more instructions in the packet are executed. Whether the control word is short or long will depend upon the situation. A short control word will be included in the packet in the event that the short control word has a sufficient number of content bits for support of a feature that influences how one or more instructions in the packet are executed. However, a long control word will be included in the packet instead of the short control word in the event that the short control word has an insufficient number of content bits for support of the feature and the long control word has a sufficient number of content bits for support of the feature. ## Claims ### Claim 1 A processor comprising: two or more clusters having functional units; and a program control unit to decode instruction packets, at least one of the packets including one or more instructions and one or more control words, where a control word support a feature that influences how one or more instructions in the packet are executed by the functional units, wherein for certain features, short control words provide full support of the features in a processor having at most two clusters and long control words provide full support of the feature in a processor having more that two clusters. ### Claim 2 (depends on 1) The processor of claim 1, wherein the processor is a digital signal processor. ### Claim 3 (depends on 1) The processor of claim 1, wherein the clusters have registers and one of the certain features is an ability to read a register of a different cluster for use as an operand. ### Claim 4 (depends on 1) The processor of claim 1, wherein one of the certain features is instruction replication. ### Claim 5 (depends on 1) The processor of claim 1, wherein one of the certain features is instruction relocation. ### Claim 6 A method for including a short control word or a long control word in a instruction packet, the method comprising: including a short control word in the packet in the event that the short control word has a sufficient number of content bits for support of a feature that influences how one or more instructions is the packet are executed; and including a long control word in the packet in the event that the short control word has and insufficient number of content bits for support of the feature and the long control word has a sufficient number of content bits for support of the feature. ### Claim 7 (depends on 6) The method of claim 6, wherein the feature is instruction replication. ### Claim 8 (depends on 6) The method of claim 6, wherein the feature is instruction relocation. ### Claim 9 (depends on 6) The method of claim 6, wherein the feature is extension of an immediate operand of an instruction. ### Claim 10 (depends on 6) The method of claim 6, wherein the feature is extension of an operation of an instruction. ### Claim 11 (depends on 6) The method of claim 6, wherein the feature is extension of an address operand of an instruction. ### Claim 12 A method for including one or more control words in an instruction packet, where a control word supports a feature that influences how one or more instructions in the packet are executed, the method comprising: including a short control word in the packet in the event that the specific instructions in the packet that are influenced by the short control word relate to no more than two clusters; and including a long control word in the packet in the event that the specific instructions in the packet that are influenced by the long control word relate to more than two clusters. ### Claim 13 (depends on 12) The method of claim 12, wherein the feature is an ability to read a register of a different cluster for use as an operand. ### Claim 14 (depends on 12) The method of claim 12, wherein the feature is instruction replication. ### Claim 15 (depends on 12) The method of claim 12, wherein the feature is instruction relocation. ### Claim 16 A method comprising: providing a processor architecture having a configurable number of clusters of functional units; and providing a set of instructions for use in the architecture so that different processors having different numbers of clusters can use the same set of instructions, including providing a set of control words to influence how the instructions are executed in the processor, where the set of control words includes: a short control word to support a feature in processors having two clusters; and a long control word to support the feature in processors having four clusters. ### Claim 17 (depends on 16) The method of claim 16, wherein the feature is an ability to read a register of a different cluster for use as an operand. ### Claim 18 (depends on 16) The method of claim 16, wherein the feature is instruction replication. ### Claim 19 (depends on 16) The method of claim 16, wherein the feature is instruction relocation. ### Claim 20 A method comprising: providing a processor architecture having a configurable native data width; and providing a set of instructions for use in the architecture so that different processors having different native data widths can use the same set of instructions, including: a) providing a set of control words to influence how the instructions are executed in the processor; and b) allocating a particular number of bits in some of the instructions to encode least significant bits of an immediate operand, where the set of control words includes: a short control word to encode higher-order bits of an immediate operand for processors having a narrow native data width, and a long control word to encode higher-order bits of an immediate operand for processors having a wide native data width. ### Claim 21 (depends on 20) The method of claim 20, wherein a narrow data width is equal or less than the sum of the number of the higher-order bits and the particular number of bits. ### Claim 22 (depends on 20) The method of claim 20, wherein a wide data width is greater than the sum of the number of content bits of the short control word and the particular number of bits.