High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

A superscalar processing system for executing instructions, comprising:

• an instruction fetch unit configured to fetch a plurality of instructions from an instruction store, said plurality of instructions including more than two instructions and having a prescribed program order;
• a register file configured to store register data corresponding to said plurality of instructions;
• an instruction execution unit configured to select a subset of said plurality of instructions for execution, said instruction execution unit being configured to select said subset of said plurality of instructions from among any combination of two or more of said plurality of instructions, said instruction execution unit comprising a plurality of functional units, each of said plurality of functional units configured to execute a corresponding one of said subset of said plurality of instructions and to generate results data therefrom;
• a register file output bus configured to concurrently transfer register data associated with said subset of said plurality of instructions from said register file to said plurality of functional units for use in execution of said subset of said plurality of instructions;
• and
• an output bus configured to concurrently distribute said results data to said register file.

A method for executing instructions in a superscalar processing system, comprising:

• concurrently fetching a plurality of instructions from an instruction store, said plurality of instructions including more than two instructions and having a prescribed program order;
• storing register data corresponding to said plurality of instructions in a register file;
• selecting a subset of said plurality of instructions for execution, wherein said subset of said plurality of instructions is selected from among any combination of two or more of said plurality of instructions;
• concurrently transferring register data associated with said subset of said plurality of instructions from said register file to a plurality of functional units;
• executing each instruction in said subset of said plurality of instructions in a corresponding one of said plurality of functional units to generate results data therefrom;
• and
• concurrently distributing said results data to said register file.

A computer system, comprising:

• a memory;
• a superscalar microprocessor;
• and
• a bus coupled between the memory and the microprocessor;
• wherein said microprocessor includes:
• an instruction fetch unit configured to fetch a plurality of instructions from said memory, said plurality of instructions including more than two instructions and having a prescribed program order,
• a register file configured to store register data corresponding to said plurality of instructions,
• an instruction execution unit configured to select a subset of said plurality of instructions for execution, said instruction execution unit being configured to select said subset of said plurality of instructions from among any combination of two or more of said plurality of instructions, said instruction execution unit comprising a plurality of functional units, each of said plurality of functional units configured to execute a corresponding one of said subset of said plurality of instructions and to generate results data therefrom,
• a register file output bus configured to concurrently transfer register data associated with said subset of said plurality of instructions from said register file to said plurality of functional units for use in execution of said subset of said plurality of instructions, and
• an output bus configured to concurrently distribute said results data to said register file.