Back to results
US 2006/0149924 A1Published application
Evaluation unit for single instruction, multiple data execution engine flag registers
AssigneeIntel Corporation
InventorsMichael Dwyer, Hong Jiang
Life of this patent
Estimating the term…
Abstract
According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by the SIMD execution engine. According to some embodiments, a vertical evaluation unit might perform evaluation operations across multiple flag registers.
Claims29
A method, comprising:
- storing information into a n-location flag register of an n-channel Single Instruction, Multiple-Data (SIMD) execution engine, the information representing multiple m-channel independent vectors, where n and m are integers greater than one;
- and
- generating an output based on the information in the flag register, the output including at least one location whose value is based on information representing different independent vectors.
A method, comprising:
- storing information into a first p-location flag register of an n-channel Single Instruction, Multiple-Data (SIMD) execution engine, wherein n and p are integers greater than one;
- storing information into a second flag register of the execution engine;
- and
- generating an output, the output including at least one location whose value is based on information from both the first flag register and the second flag register.
1 more element
A method, comprising:
- storing information into a flag register of an n-channel Single Instruction, Multiple-Data (SIMD) execution engine, where n is an integer greater than one;
- receiving an indication associated with a set of SIMD execution engine channels;
- and
- generating an output based on the information in the flag register associated with the set of SIMD execution engine channels.
1 more element
An apparatus, comprising:
- a n-bit flag register of an n-channel Single Instruction, Multiple-Data (SIMD) execution engine, where n is an integer greater than one and each bit of the flag register is associated with a channel, and wherein the flag register is to store information from an execution unit, the information to be associated with more than one multiple-channel graphics vector;
- and
- a horizontal evaluation unit to generate an n-bit output, wherein each bit in the output is associated with a channel of the SIMD execution engine, and a value of at least one bit in the output is to be based on bits in the flag register that represent different graphics vectors.
An apparatus, comprising:
- a first n-bit flag register of an n-channel Single Instruction, Multiple-Data (SIMD) execution engine, wherein n is an integer greater than one;
- a second n-bit flag register of the SIMD execution engine;
- and
- a vertical evaluation unit to generate an n-bit output, the output including at least one bit whose value is based on information from both the first flag register and the second flag register.
1 more element
A system, comprising:
- a processor, including:
- an n-channel Single Instruction, Multiple-Data (SIMD) execution engine,
- wherein n is an integer greater than one, including:
- a first n-bit flag register,
- a second n-bit flag register, and
- a vertical evaluation unit to generate an n-bit output, the output including at least one bit whose value is based on information from both the first flag register and the second flag register;
- and
- a graphics memory unit.
5 more elements
Dependencies are inferred from the claim text.