Microprocessor optimized for algorithmic processing

A processing unit comprising:

• a primary processor having an arithmetic logic unit and data memory cache;
• one or more subprocessors;
• one or more memory data stores, each of the memory data stores associated with at least one of the one or more subprocessors;
• a buss connecting the arithmetic logic unit of the primary processor to the data memory cache of the primary processor and to the one or more memory data stores.

A method of processing an algorithm on a multiple-processor system, the method comprising the steps:

• connecting, with a crossbar buss, an arithmetic logic unit on a primary processor to a data cache on the primary processor;
• connecting, with the crossbar buss, the arithmetic logic unit on the primary processor to a first data memory store associated with a first subprocessor;
• loading data intended to be processed by the first subprocessor into the first data memory store;
• connecting, with the crossbar buss, the arithmetic logic unit on the primary processor to a first instruction memory store associated with the first subprocessor;
• loading instructions intended to be executed by the first subprocessor into the first instruction memory store;
• connecting, with the crossbar buss, the arithmetic logic unit on the primary processor to a second data memory store associated with a second subprocessor;
• loading data intended to be processed by the second subprocessor into the second data memory store;
• connecting, with the crossbar buss, the arithmetic logic unit on the primary processor to a second instruction memory store associated with the second subprocessor;
• loading instructions intended to be executed by the second subprocessor into the second instruction memory store.