Method and apparatus for sharing control components across multiple processing elements

A apparatus, comprising:

• first and second processing cores, each including a respective datapath and register file;
• a control store to store instructions;
• an instruction control unit, coupled to receive instructions from the control store, to decode the instructions;
• and
• instruction gating logic, communicately-coupled between the instruction control unit and the datapaths, to selectively forward decoded instructions received from the instruction control unit to the first and second datapaths.

A network processor, comprising:

• an internal interconnect comprising sets of bus lines via which data and control signals are passed;
• at least one combined microengine, each combined microengine operatively-coupled to the internal interconnect and including,
• first and second processing cores, each including a respective datapath and register file;
• a shared control store to store instructions;
• a shared instruction control unit, coupled to receive instructions from the shared control store, to decode the instructions;
• and
• instruction gating logic, defined between the instruction control unit and the datapaths, to selectively forward decoded instructions received from the instruction control unit to the first and second datapaths;
• and
• a least one memory controller, operatively coupled to the internal interconnect.

A network line card, comprising:

• a network processor, including,
• an internal interconnect comprising sets of bus lines via which data and control signals are passed;
• at least one combined microengine, each combined microengine operatively-coupled to the internal interconnect and including,
• first and second processing cores, each including a respective datapath and register file;
• a shared control store to store instructions;
• a shared instruction control unit, coupled to receive instructions from the shared control store, to decode the instructions;
• and
• instruction gating logic, defined between the instruction control unit and the datapaths, to selectively forward decoded instructions received from the instruction control unit to the first and second datapaths;
• a backplane interface including a media switch fabric interface communicatively-coupled to the internal interconnect.