# US 2006/0149919 A1 · Method, system, and program for addressing pages of memory by an I/O device

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- Number: US 2006/0149919 A1
- Document ID: US20060149919A1
- Status: Published application
- Kind: A1
- Application number: 11/029,917
- Filed: 2005-01-05
- Published: 2006-07-06
- Earliest claimed: 2005-01-05
- Assignees: Intel Corporation
- Inventors: Arturo Arizpe; Gary Tsao
- Web page: https://patentgrep.com/patent/US20060149919A1

## CPC

- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 12/1009: using page tables, e.g. page table structures
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical address is stored in a data structure table for each page. Each virtual address includes a page virtual address which identifies the translation entry containing the physical address of the page containing the memory location. The virtual address may be translated to a translation entry index using the size of the page containing the memory location.

## Claims

### Claim 1

A method, comprising:
identifying a plurality of pages of memory locations allocated to an input/output (I/O) device, wherein the memory locations within each page are contiguous and wherein a plurality of said pages are of different sizes; and
for each identified page, storing in a translation entry of a data structure table, a physical address of an identified page.

### Claim 2 (depends on 1)

The method of claim 1 further comprising assigning each identified page a page virtual address which identifies a data structure translation entry in which is stored the physical address of the identified page.

### Claim 3 (depends on 2)

The method of claim 2 further comprising assigning each memory location a memory location virtual address which includes the page virtual address of the page containing the memory location, and a physical address offset relative to the page physical address of the page containing the memory location.

### Claim 4 (depends on 3)

The method of claim 3 wherein the size of the page containing the memory location addressed by a memory location virtual address is equal to 2P memory locations and the physical address offset of the memory location addressed by the memory location virtual address is defined by the P least significant bits of the virtual address.

### Claim 5 (depends on 4)

The method of claim 4 wherein the assigned virtual addresses define a virtual address space which includes a plurality of blocks of virtual addresses and wherein the virtual addresses assigned to memory pages of the same size are within the same block of virtual addresses.

### Claim 6 (depends on 5)

The method of claim 5 wherein the data structure table has a plurality of segments of translation entries, wherein for each translation entry of a particular segment, the size of the page addressed by each entry of the particular segment is the same.

### Claim 7 (depends on 6)

The method of claim 6 wherein each data structure table segment of translation entries is assigned a base virtual address of said virtual address space.

### Claim 8 (depends on 7)

The method of claim 7 wherein each data structure table segment of translation entries is assigned a base translation entry index which for a particular data structure table segment, equals the number of translation entries for pages of greater size than the size of the pages addressed by the translation entries of the particular data structure table segment.

### Claim 9 (depends on 8)

The method of claim 8 wherein the virtual address of each memory location includes a translation entry index offset which when combined with a base translation entry index, identifies the translation entry containing the physical address of the page of memory locations containing the memory location addressed by the virtual address.

### Claim 10 (depends on 9)

The method of claim 9 further comprising translating the memory location virtual address of a particular memory location to the physical address of the particular memory location.

### Claim 11 (depends on 10)

The method of claim 10 wherein the memory location virtual address translating includes translating the page virtual address of the memory location virtual address to the physical address of a particular page of memory locations containing the particular memory location.

### Claim 12 (depends on 11)

The method of claim 11 wherein the memory location virtual address translating includes combining the physical address of the particular page of memory locations with the physical address offset within the particular page of memory locations to identify the physical address of the particular memory location.

### Claim 13 (depends on 12)

The method of claim 12 wherein the page virtual address translating includes translating the page virtual address of the particular page of memory locations to a base translation entry index which identifies a particular data structure table segment and to a translation entry index offset which identifies a particular data structure translation entry within the particular data structure table segment wherein the particular data structure translation entry contains the physical address of the particular page of memory locations.

### Claim 14 (depends on 13)

The method of claim 13 wherein the page virtual address translating includes identifying the size of the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 15 (depends on 14)

The method of claim 14 wherein said page size identifying includes identifying the virtual address space portion containing the memory location virtual address of the particular memory location.

### Claim 16 (depends on 15)

The method of claim 15 wherein the physical address identifying includes identifying the base virtual address of the data structure table segment containing the translation entry for the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 17 (depends on 16)

The method of claim 16 wherein said translation entry index offset translating includes subtracting the identified base virtual address of the data structure table segment, from the memory location virtual address of the particular memory location to provide a virtual address offset and shifting the virtual address offset P bits to the right to derive the translation entry index offset, and wherein the page virtual address translating includes combining the derived translation entry index offset with the base translation entry index to provide a translation entry index which identifies the translation entry containing the physical address of the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 18 (depends on 17)

The method of claim 17 wherein said memory location virtual address translating includes reading the page physical address at the translation entry at the identified translation entry index and adding to the read page physical address, the physical address offset of the memory location virtual address of the particular memory location.

### Claim 19

An input/output (I/O) device for use with a memory having a plurality of memory locations, comprising:
logic adapted to:
maintain a data structure table comprising a plurality of translation entries;
identify a plurality of pages of said memory locations allocated to said I/O device, wherein the memory locations within each page are contiguous and wherein a plurality of said pages are of different sizes; and
for each identified page, store in a translation entry of said data structure table, a physical address of an identified page.

### Claim 20 (depends on 19)

The I/O device of claim 19 wherein the logic is further adapted to assign each identified page a page virtual address which identifies a data structure translation entry in which is stored the physical address of the identified page.

### Claim 21 (depends on 20)

The I/O device of claim 20 wherein the logic is further adapted to assign each memory location a memory location virtual address which includes the page virtual address of the page containing the memory location, and a physical address offset relative to the page physical address of the page containing the memory location.

### Claim 22 (depends on 21)

The I/O device of claim 21 wherein the size of the page containing the memory location addressed by a memory location virtual address is equal to 2P memory locations and the physical address offset of the memory location addressed by the memory location virtual address is defined by the P least significant bits of the virtual address.

### Claim 23 (depends on 22)

The I/O device of claim 22 wherein the assigned virtual addresses define a virtual address space which includes a plurality of blocks of virtual addresses and wherein the virtual addresses assigned to memory pages of the same size are within the same block of virtual addresses.

### Claim 24 (depends on 23)

The I/O device of claim 23 wherein the data structure table has a plurality of segments of translation entries, wherein for each translation entry of a particular segment, the size of the page addressed by each entry of the particular segment is the same.

### Claim 25 (depends on 24)

The I/O device of claim 24 wherein each data structure table segment of translation entries is assigned a base virtual address of said virtual address space.

### Claim 26 (depends on 25)

The I/O device of claim 25 wherein each data structure table segment of translation entries is assigned a base translation entry index which for a particular data structure table segment, equals the number of translation entries for pages of greater size than the size of the pages addressed by the translation entries of the particular data structure table segment.

### Claim 27 (depends on 26)

The I/O device of claim 26 wherein the virtual address of each memory location includes a translation entry index offset which when combined with a base translation entry index, identifies the translation entry containing the physical address of the page of memory locations containing the memory location addressed by the virtual address.

### Claim 28 (depends on 27)

The I/O device of claim 27 wherein the logic is further adapted to translate the memory location virtual address of a particular memory location to the physical address of the particular memory location.

### Claim 29 (depends on 28)

The I/O device of claim 28 wherein the memory location virtual address translating includes translating the page virtual address of the memory location virtual address to the physical address of a particular page of memory locations containing the particular memory location.

### Claim 30 (depends on 29)

The I/O device of claim 29 wherein the memory location virtual address translating includes combining the physical address of the particular page of memory locations with the physical address offset within the particular page of memory locations to identify the physical address of the particular memory location.

### Claim 31 (depends on 30)

The I/O device of claim 30 wherein the page virtual address translating includes translating the page virtual address of the particular page of memory locations to a base translation entry index which identifies a particular data structure table segment and to a translation entry index offset which identifies a particular data structure translation entry within the particular data structure table segment wherein the particular data structure translation entry contains the physical address of the particular page of memory locations.

### Claim 32 (depends on 31)

The I/O device of claim 31 wherein the page virtual address translating includes identifying the size of the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 33 (depends on 32)

The I/O device of claim 32 wherein said page size identifying includes identifying the virtual address space portion containing the memory location virtual address of the particular memory location.

### Claim 34 (depends on 33)

The I/O device of claim 33 wherein the physical address identifying includes identifying the base virtual address of the data structure table segment containing the translation entry for the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 35 (depends on 34)

The I/O device of claim 34 wherein said translation entry index offset translating includes subtracting the identified base virtual address of the data structure table segment, from the memory location virtual address of the particular memory location to provide a virtual address offset and shifting the virtual address offset P bits to the right to derive the translation entry index offset, and wherein the page virtual address translating includes combining the derived translation entry index offset with the base translation entry index to provide a translation entry index which identifies the translation entry containing the physical address of the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 36 (depends on 35)

The I/O device of claim 35 wherein said memory location virtual address translating includes reading the page physical address at the translation entry at the identified translation entry index and adding to the read page physical address, the physical address offset of the memory location virtual address of the particular memory location.

### Claim 37

A system for use with a memory having a plurality of memory locations, comprising:
at least one memory which includes an operating system;
a motherboard;
a processor mounted on the motherboard and coupled to the memory;
an expansion card coupled to said motherboard;
a controller mounted on said expansion card wherein said memory includes a plurality of memory locations adapted to be allocated to said controller; and
a device driver executable by the processor in the memory for said controller wherein the device driver is adapted to:
maintain in said memory a data structure table comprising a plurality of translation entries;
identify a plurality of pages of said memory locations allocated to said controller, wherein the memory locations within each page are contiguous and wherein a plurality of said pages are of different sizes; and
for each identified page, store in a translation entry of said data structure table, a physical address of an identified page.

### Claim 38 (depends on 37)

The system of claim 37 wherein the driver is further adapted to assign each identified page a page virtual address which identifies a data structure translation entry in which is stored the physical address of the identified page.

### Claim 39 (depends on 38)

The system of claim 38 wherein the driver is further adapted to assign each memory location a memory location virtual address which includes the page virtual address of the page containing the memory location, and a physical address offset relative to the page physical address of the page containing the memory location.

### Claim 40 (depends on 39)

The system of claim 39 wherein the size of the page containing the memory location addressed by a memory location virtual address is equal to 2P memory locations and the physical address offset of the memory location addressed by the memory location virtual address is defined by the P least significant bits of the virtual address.

### Claim 41 (depends on 40)

The system of claim 40 wherein the assigned virtual addresses define a virtual address space which includes a plurality of blocks of virtual addresses and wherein the virtual addresses assigned to memory pages of the same size are within the same block of virtual addresses.

### Claim 42 (depends on 41)

The system of claim 41 wherein the data structure table has a plurality of segments of translation entries, wherein for each translation entry of a particular segment, the size of the page addressed by each entry of the particular segment is the same.

### Claim 43 (depends on 42)

The system of claim 42 wherein each data structure table segment of translation entries is assigned a base virtual address of said virtual address space.

### Claim 44 (depends on 43)

The system of claim 43 wherein each data structure table segment of translation entries is assigned a base translation entry index which for a particular data structure table segment, equals the number of translation entries for pages of greater size than the size of the pages addressed by the translation entries of the particular data structure table segment.

### Claim 45 (depends on 44)

The system of claim 44 wherein the virtual address of each memory location includes a translation entry index offset which when combined with a base translation entry index, identifies the translation entry containing the physical address of the page of memory locations containing the memory location addressed by the virtual address.

### Claim 46 (depends on 45)

The system of claim 45 wherein the controller is adapted to translate the memory location virtual address of a particular memory location to the physical address of the particular memory location.

### Claim 47 (depends on 46)

The system of claim 46 wherein the memory location virtual address translating includes translating the page virtual address of the memory location virtual address to the physical address of a particular page of memory locations containing the particular memory location.

### Claim 48 (depends on 47)

The system of claim 47 wherein the memory location virtual address translating includes combining the physical address of the particular page of memory locations with the physical address offset within the particular page of memory locations to identify the physical address of the particular memory location.

### Claim 49 (depends on 47)

The system of claim 47 wherein the page virtual address translating includes translating the page virtual address of the particular page of memory locations to a base translation entry index which identifies a particular data structure table segment and to a translation entry index offset which identifies a particular data structure translation entry within the particular data structure table segment wherein the particular data structure translation entry contains the physical address of the particular page of memory locations.

### Claim 50 (depends on 49)

The system of claim 49 wherein the page virtual address translating includes identifying the size of the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 51 (depends on 50)

The system of claim 50 wherein said page size identifying includes identifying the virtual address space portion containing the memory location virtual address of the particular memory location.

### Claim 52 (depends on 51)

The system of claim 51 wherein the physical address identifying includes identifying the base virtual address of the data structure table segment containing the translation entry for the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 53 (depends on 52)

The system of claim 52 wherein said translation entry index offset translating includes subtracting the identified base virtual address of the data structure table segment, from the memory location virtual address of the particular memory location to provide a virtual address offset and shifting the virtual address offset P bits to the right to derive the translation entry index offset, and wherein the page virtual address translating includes combining the derived translation entry index offset with the base translation entry index to provide a translation entry index which identifies the translation entry containing the physical address of the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 54 (depends on 53)

The system of claim 53 wherein said memory location virtual address translating includes reading the page physical address at the translation entry at the identified translation entry index and adding to the read page physical address, the physical address offset of the memory location virtual address of the particular memory location.

### Claim 55

An article comprising a storage medium for use with a controller and a memory having a plurality of memory locations, wherein the storage medium comprises machine readable instructions stored thereon to:
maintain a data structure table comprising a plurality of translation entries;
identify a plurality of pages of said memory locations allocated to said controller, wherein the memory locations within each page are contiguous and wherein a plurality of said pages are of different sizes; and
for each identified page, store in a translation entry of said data structure table, a physical address of an identified page.

### Claim 56 (depends on 55)

The article of claim 55 wherein the storage medium further comprises machine readable instructions stored thereon to:
assign each identified page a page virtual address which identifies a data structure translation entry in which is stored the physical address of the identified page; and
assign each memory location a memory location virtual address which includes the page virtual address of the page containing the memory location, and a physical address offset relative to the page physical address of the page containing the memory location;
wherein the size of the page containing the memory location addressed by a memory location virtual address is equal to 2P memory locations and the physical address offset of the memory location addressed by the memory location virtual address is defined by the P least significant bits of the virtual address, the assigned virtual addresses define a virtual address space which includes a plurality of blocks of virtual addresses and wherein the virtual addresses assigned to memory pages of the same size are within the same block of virtual addresses; and
wherein the data structure table has a plurality of segments of translation entries, wherein for each translation entry of a particular segment, the size of the page addressed by each entry of the particular segment is the same, each data structure table segment of translation entries is assigned a base virtual address of said virtual address space, each data structure table segment of translation entries is assigned a base translation entry index which for a particular data structure table segment, equals the number of translation entries for pages of greater size than the size of the pages addressed by the translation entries of the particular data structure table segment, and the virtual address of each memory location includes a translation entry index offset which when combined with a base translation entry index, identifies the translation entry containing the physical address of the page of memory locations containing the memory location addressed by the virtual address.

### Claim 57 (depends on 56)

The article of claim 56 wherein the storage medium further comprises machine readable instructions stored thereon to translate the memory location virtual address of a particular memory location to the physical address of the particular memory location.

### Claim 58 (depends on 57)

The article of claim 57 wherein the memory location virtual address translating includes translating the page virtual address of the memory location virtual address to the physical address of a particular page of memory locations containing the particular memory location, the memory location virtual address translating includes combining the physical address of the particular page of memory locations with the physical address offset within the particular page of memory locations to identify the physical address of the particular memory location, the page virtual address translating includes translating the page virtual address of the particular page of memory locations to a base translation entry index which identifies a particular data structure table segment and to a translation entry index offset which identifies a particular data structure translation entry within the particular data structure table segment wherein the particular data structure translation entry contains the physical address of the particular page of memory locations, and the page virtual address translating includes identifying the size of the particular page containing the particular memory location addressed by the memory location virtual address.

### Claim 59 (depends on 58)

The article of claim 58 wherein said page size identifying includes identifying the virtual address space portion containing the memory location virtual address of the particular memory location, the physical address identifying includes identifying the base virtual address of the data structure table segment containing the translation entry for the particular page containing the particular memory location addressed by the memory location virtual address, said translation entry index offset translating includes subtracting the identified base virtual address of the data structure table segment, from the memory location virtual address of the particular memory location to provide a virtual address offset and shifting the virtual address offset P bits to the right to derive the translation entry index offset, and wherein the page virtual address translating includes combining the derived translation entry index offset with the base translation entry index to provide a translation entry index which identifies the translation entry containing the physical address of the particular page containing the particular memory location addressed by the memory location virtual address, and said memory location virtual address translating includes reading the page physical address at the translation entry at the identified translation entry index and adding to the read page physical address, the physical address offset of the memory location virtual address of the particular memory location.