Secure memory controller
OwnerDennis O'Connor, Mark Fullerton +1inventors
InventorsDennis O'Connor, Mark Fullerton, Ray Richardson
Life of this patent
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Abstract
A memory controller partitions memory into secure partitions and non-secure partitions.
Claims30
A memory controller comprising a memory partitioning mechanism to partition memory into secure and non-secure partitions wherein the memory partitioning mechanism comprises at least one register to define a range of locations in a memory.
A memory controller comprising a memory partitioning mechanism to partition memory into partitions with varying levels of security wherein the memory partitioning mechanism comprises registers sufficient to define a range of locations in a memory for each level of security.
An integrated circuit comprising:
- a processor;
- a memory controller including a mechanism to partition a memory into secure and non-secure partitions;
- and
- a bus interconnecting the processor and the memory controller, the bus including a signal path to identify a security status of a memory transaction.
A method comprising:
- determining if a memory transaction is a secure transaction;
- and
- comparing a target address of the memory transaction to a value in a range register to determine if the target address is in secure memory.
A system comprising:
- an antenna;
- a receiver coupled to the antenna;
- and
- an integrated circuit coupled to the receiver, the integrated circuit including a processor a memory controller having a mechanism to partition a memory into secure and non-secure partitions, and a bus interconnecting the processor and the memory controller, the bus including a signal path to identify a security status of a memory transaction.
Dependencies are inferred from the claim text.