US 2006/0149903 A1Published application

Fault tolerant computer system and a synchronization method for the same

AssigneeNEC Corporation

InventorMotohiro Sugimoto

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Abstract

Each time a sync controller sequentially issues a read request to a memory controller, a count value of a first counter is incremented. When a read operation is conducted for the read request, a count value of a second counter is incremented and the data is transferred to a standby computer. If a memory write instruction is issued during a memory copy operation, an address comparator compares a write address of the memory write instruction with the count values of the first and second counters. If the write address is more than the count values, the memory write operation is permitted. If the write address is equal to the count value of the first counter, the process waits for termination of the data read operation. Otherwise, the write operation is immediately permitted and the write data is transferred to the sync controller. Data of a memory on the active side can be hence copied onto the standby computer without stopping the system operation.

Claims12

Dependent claims

A fault tolerant computer system, comprising a plurality of computer systems each of which comprises:

one processor or a plurality of processors;
a main memory;
a routine controller;
a sync controller;
and
a bridge circuit connecting the processors, the main memory, the routine controller, and the sync controller to each other to control the constituent components, wherein the respective computer systems are synchronized and process the same instruction string, wherein:
when data of a main memory of a first computer system is copied onto a main memory of a second computer system, the data is read via a sync controller from the main memory to be transferred to a sync controller of the second computer system;
the routing controller comprises a memory access monitor unit including a counter module which determines, when the data is read via the sync controller from the main memory, a state of a process of the read operation, and an address comparator to compare, when the processor issues a write instruction, a counter value of the counter module with a write address for which a writing operation is conducted by the write instruction;
and
when the processor issues a write instruction for the main memory during an operation in which in order to synchronize a standby computer system, which is in a non-operating state, with an active computer system, which is in an operating state, data of the main memory of the active computer system is sequentially transferred to the standby computer system;
the memory access monitor unit transfers, according to a result of a comparison conducted by the address comparator, to the sync controller of the active computer system only write data of an address for which a data read operation has already been completed and write data of an address for which a data read operation is being currently conducted.

8 more elements

A fault tolerant computer system, comprising a plurality of computer systems each of which comprises:

one processor or a plurality of processors;
a main memory;
a routine controller;
a sync controller;
and
a bridge circuit connecting the processors, the main memory, the routine controller, and the sync controller to each other to control the constituent components, wherein the respective computer systems are synchronized and process the same instruction string, wherein:
when data of a main memory of a first computer system is copied onto a main memory of a second computer system, the data is read via a sync controller from the main memory to be transferred to a sync controller of the second computer system;
the routing controller comprises a memory access monitor unit including a counter module which determines, when the data is read via the sync controller from the main memory, a state of a process of the read operation and an address comparator to compare, when the processor issues a write instruction, a counter value of the counter module with a write address for which a writing operation is conducted by the write instruction;
and
when the processor issues a write instruction for the main memory during an operation in which to synchronize a standby computer system with an active computer system, data of the main memory of the active computer system is sequentially transferred to the standby computer system;
the memory access monitor unit executes, if the write instruction is issued for an address for which a data read operation is completed or for which a data read operation is currently in process according to a result of a comparison conducted by the address comparator, the write instruction and notifies an interrupt, and the sync controller obtains the write data in an operation of executing interrupt processing of the interrupt thus notified.

8 more elements

A synchronization method of synchronizing a standby computer system with an active computer system for use with a fault tolerant computer system comprising a plurality of computer systems each of which comprises one processor or a plurality of processors, a main memory, a routine controller, a sync controller, and a bridge circuit connecting the processors, the main memory, the routine controller, and the sync controller to each other to control the constituent components, wherein the respective computer systems process one and the same instruction string at timing synchronized with a clock signal, wherein:

when data of a main memory of an active computer system is copied onto a main memory of a standby computer system, if a write instruction is issued for an address for which a data transfer operation is completed or for an address for which a read operation is started to transfer data to the standby computer system, data of the write instruction is transferred to the standby computer system to thereby synchronize the standby computer system with the active computer system without stopping the active computer system.

Dependencies are inferred from the claim text.