Flash memory programming

A flash memory device, comprising:

• an array of flash memory cells;
• a volatile storage media;
• and
• control circuitry for controlling access to the array of flash memory cells, wherein the control circuitry is adapted to perform a method, the method comprising:
• receiving a block of words from an external processor into the volatile storage media in response to a write command;
• after receiving the block of words into the volatile storage media, programming the block of words into the array of flash memory cells in parallel without the need for further input from the external processor;
• after programming the block of words into the array of flash memory cells, comparing data values in the array of flash memory cells against data values in the volatile storage media;
• and
• reprogramming any word that has a data value in the array of flash memory cells that does not match its corresponding data value in the volatile storage media.

A floating-gate memory device, comprising:

• an array of floating-gate memory cells;
• a static random access memory (SRAM) register;
• and
• control circuitry for controlling access to the array of floating-gate memory cells, wherein the control circuitry is adapted to perform a method, the method comprising:
• receiving a write command from an external processor;
• sequentially receiving a plurality of data words from the external processor, wherein each data word is associated with a starting address;
• storing each data word in the SRAM register;
• sequentially writing each data word from the SRAM register to the array of floating-gate memory cells;
• after writing all of the data words from the SRAM register to the array of floating-gate memory cells, preparing the floating-gate memory device to verify data values in the array of floating-gate memory cells;
• and
• verifying the data values in the array of floating-gate memory cells by comparing each data value of a word in the array of floating-gate memory cells with a corresponding word in the SRAM register and rewriting any word in the array of floating-gate memory cells that does not match its corresponding word in the SRAM register without the need for further input from the external processor.

A floating-gate memory device, comprising:

• an array of floating-gate memory cells;
• a static random access memory (SRAM) register;
• and
• control circuitry for controlling access to the array of floating-gate memory cells, wherein the control circuitry is adapted to perform a method, the method comprising:
• receiving a write command from an external processor;
• sequentially receiving a plurality of data words from the external processor, wherein each data word is associated with a starting address;
• storing each data word in the SRAM register;
• writing the data words from the SRAM register to the array of floating-gate memory cells in parallel in response to the write command;
• after writing the data words from the SRAM register to the array of floating-gate memory cells, preparing the floating-gate memory device to verify data values in the array of floating-gate memory cells;
• and
• verifying the data values in the array of floating-gate memory cells by comparing each data value of a word in the array of floating-gate memory cells with a corresponding word in the SRAM register and rewriting any word in the array of floating-gate memory cells that does not match its corresponding word in the SRAM register.

An electronic system, comprising:

• a processor;
• and
• one or more flash memory devices coupled to the processor, wherein at least one of the flash memory devices comprises:
• an array of flash memory cells;
• volatile storage media;
• and
• control circuitry for controlling access to the array of flash memory cells, wherein the control circuitry is adapted to perform a method, the method comprising:
• receiving a plurality of words from the processor into the volatile storage media;
• after receiving the plurality of words into the volatile storage media, programming each word sequentially into the array of flash memory cells;
• after programming the plurality of words into the array of flash memory cells, comparing data values in the array of flash memory cells against data values in the volatile storage media;
• and
• reprogramming any word that has a data value in the array of flash memory cells that does not match its corresponding data value in the volatile storage media without the need for further input from the processor.

An electronic system, comprising:

• a processor;
• and
• one or more flash memory devices coupled to the processor, wherein at least one of the flash memory devices comprises:
• an array of flash memory cells;
• a volatile storage media;
• and
• control circuitry for controlling access to the array of flash memory cells, wherein the control circuitry is adapted to perform a method, the method comprising:
• receiving a write command from the processor;
• receiving a plurality of words from the processor into the volatile storage media;
• and
• after receiving the plurality of words into the volatile storage media, programming the plurality of words into the array of flash memory cells in parallel in response to the write command.

An electronic system, comprising:

• a processor;
• and
• one or more floating-gate memory devices coupled to the processor, wherein at least one of the floating-gate memory devices comprises:
• an array of floating-gate memory cells;
• a static random access memory (SRAM) register;
• and
• control circuitry for controlling access to the array of floating-gate memory cells, wherein the control circuitry is adapted to perform a method, the method comprising:
• receiving a write command from the processor;
• sequentially receiving a plurality of data words from the processor, wherein each data word is associated with a starting address;
• storing each data word in the SRAM register;
• sequentially writing each data word from the SRAM register to the array of floating-gate memory cells;
• after writing all of the data words from the SRAM register to the array of floating-gate memory cells, preparing the floating-gate memory device to verify data values in the array of floating-gate memory cells;
• and
• verifying the data values in the array of floating-gate memory cells by comparing each data value of a word in the array of floating-gate memory cells with a corresponding word in the SRAM register and rewriting any word in the array of floating-gate memory cells that does not match its corresponding word in the SRAM register without the need for further input from the processor.

An electronic system, comprising:

• a processor;
• and
• one or more floating-gate memory devices coupled to the processor, wherein at least one of the floating-gate memory devices comprises:
• an array of floating-gate memory cells;
• a static random access memory (SRAM) register;
• and
• control circuitry for controlling access to the array of floating-gate memory cells, wherein the control circuitry is adapted to perform a method, the method comprising:
• receiving a write command from the processor;
• sequentially receiving a plurality of data words from the processor, wherein each data word is associated with a starting address;
• storing each data word in the SRAM register;
• writing the data words from the SRAM register to the array of floating-gate memory cells in parallel in response to the write command;
• after writing the data words from the SRAM register to the array of floating-gate memory cells, preparing the floating-gate memory device to verify data values in the array of floating-gate memory cells;
• and
• verifying the data values in the array of floating-gate memory cells by comparing each data value of a word in the array of floating-gate memory cells with a corresponding word in the SRAM register and rewriting any word in the array of floating-gate memory cells that does not match its corresponding word in the SRAM register.