On-chip data grouping and alignment
AssigneeSanDisk Corporation
InventorSergey Gorobets
Life of this patent
Estimating the term…
Abstract
The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability to realign data sectors within a register.
Claims47
A method of operating a memory system including a memory array, comprising:
- reading a first multi-sector page of data from the memory array to a first data register;
- and
- selectively transferring less than all of the sectors of the first page of data from the first data register to a second data register.
A method of operating a memory system including a memory array, comprising:
- accessing a first multi-sector page of data from the memory array;
- and
- selectively transferring less than all of the sectors of the first page of data from the accessed first page to a first data register.
A method of operating a memory system including a memory array and a plurality of data registers, the method comprising:
- reading from the array data from a plurality of pages to the registers;
- combining within the registers data from the multiple ones of the plurality of pages into a single page in one of the registers;
- and
- writing the page of combined sectors to the memory array.
A method of operating a memory system including a plurality of memories each including a memory array and first and second data registers, the method comprising:
- performing a process in a first of said memories, including:
- reading from the first memory's array a multi-sector portion of a first page of data to the corresponding first data register;
- selectively transferring less than all of the read sectors of the first page of data from the first data register to the corresponding second data register;
- subsequent to performing said process in the first memory, moving the selectively transferred portion of the first page from the second data register of the first memory to the second data register of a second of said memories;
- subsequent to said moving the selectively transferring the portion first page of data, reading from one of the first or second memory's array a portion of a second page of data to the corresponding first data register;
- and
- transferring at least a portion of the second page of data from the corresponding first data register to the corresponding second data register while maintaining said selectively transferred sectors of the first page of data in one of said second data registers.
A method of operating a memory system including a plurality of memory arrays each having a corresponding plurality of data registers, the method comprising:
- reading from the arrays data from a plurality of meta-pages to the registers;
- combining within the registers data from the multiple ones of the plurality of meta-pages into a single meta-page in the registers;
- and
- writing the meta-page of combined sectors to the memory array.
A memory system, comprising:
- a memory chip including:
- a memory array;
- a first multi-sector register, wherein a plurality of data sectors can be transferred in parallel between the first register and the array;
- a second multi-sector register, wherein data can be transferred between the second register and externally to the memory and wherein a plurality of data sectors can be transferred in parallel between the first register and the second register,
- wherein the alignment of data sectors within one of the registers can be realigned.
A memory system, comprising:
- a first memory including:
- a memory array;
- a first multi-sector register, wherein a plurality of data sectors can be transferred in parallel between the first register and the array;
- a second multi-sector register, wherein data can be transferred between the second register and externally to the memory and wherein a plurality of data sectors can be transferred in parallel between the first register and the second register,
- wherein individual data sectors can be selectively transferred between the first register and the second register.
A memory system, comprising:
- a first memory including:
- a memory array;
- and
- a first multi-sector register, wherein a plurality of data sectors can be transferred in parallel between the first register and the array,
- wherein individual data sectors can be selectively transferred between the memory array and the first register.
Dependencies are inferred from the claim text.