Enforcing global ordering through a caching bridge in a multicore multiprocessor system
AssigneeIntel Corporation
InventorsKrishnakanth Sistla, Yen-Chen Liu, Zhong-Ning Cai
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Abstract
The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request completions may trigger corresponding snooping transactions and request completions to the cores. The order in which the transactions are observed on the system interconnect may impose the order in which the transaction triggered to the core are generated. Since this ordering is between multiple interfaces this is referred to as global ordering.
Claims25
A method for processing a request received by a bridge, comprising:
- receiving a request from a requesting core;
- processing the request;
- determining if request is owned by other agents;
- and
- sending the request to the requesting agent if request is not owned by the other agents.
A method comprising processing incoming snoops to a bridge, comprising
- allocating the incoming snoop requests in a first queue;
- determining where to send the snoop request;
- allocating the snoop request in a second queue of the requesting agent;
- and
- passing data based on the snoop request to a system interconnect.
A processor comprising:
- a caching bridge, wherein the caching bridge comprises a global ordering queue;
- a system interconnect coupled to the caching bridge;
- one or more cores coupled to the caching bridge, wherein said the global ordering queue enforces ordering for requests to and from the system interconnect to the one or more cores.
A multicore multiprocessor system comprising:
- a first processor comprising:
- a caching bridge, wherein the caching bridge comprises a global ordering queue,
- a system interconnect coupled to the caching bridge, and
- one or more cores coupled to the caching bridge, wherein said the global ordering queue enforces ordering for requests to and from the system interconnect to the one or more cores;
- a first interface to a second processor;
- a second interface coupled to input/output devices;
- and
- an audio input/output device coupled to the second interface.
Dependencies are inferred from the claim text.