Information processing device

An information processing device comprising:

• first and second bus master circuits;
• a bus to which said first and second bus master circuits are connected;
• and
• a first arbiter for arbitrating access rights of said first and second bus master circuits to said bus,
• wherein said first arbiter has a storage unit for retaining information representing priorities of said access rights of said first and second bus master circuits and a control unit for arbitrating the access rights of said first and second bus master circuits based on the information of said storage unit,
• said storage unit has flags retaining information representing whether access of said first or second bus master circuit is permitted or not,
• when the priority of said first bus master circuit is higher than the priority of said second bus master circuit and there is no access request from said first bus master circuit but there is an access request from said second bus master circuit, said control unit permits access of said second bus master circuit, and said storage unit stores, in said flag, information representing that access is permitted, and
• when access of said first bus master circuit is permitted, the priorities of said first bus master circuit and said second bus master circuit are lowered.