Efficient interrupt processing in systems with multiple serial protocol engines

An apparatus comprising:

• a plurality of protocol engines, each having an interrupt handler including:
• a plurality of interrupt inputs, a normal interrupt output and an error interrupt output, both interrupt outputs being coupled to one or more of the plurality of interrupt inputs,
• an interrupt status queue coupled to one of the plurality of interrupt inputs,
• a status register coupled to the status queue and to the normal interrupt output, and
• a normal interrupt register coupled to normal interrupt output;
• and
• a vectored interrupt control register coupled to the plurality of normal interrupt registers via an OR gate.

A process comprising:

• providing protocol engine having an interrupt handler including:
• an interrupt status queue coupled to one of a plurality of interrupt inputs,
• a status register coupled to the status queue and to the normal interrupt output, and
• a normal interrupt register coupled to normal interrupt output;
• writing a plurality of interrupts to the interrupt status queue;
• reading one or more of the interrupts from the interrupt status queue in first in, first out (FIFO) order and writing the interrupts to the status register;
• reading the one or more interrupts from the status register and writing them to the normal interrupt register;
• and
• reading the one or more interrupts from the normal interrupt register and writing them to a vectored interrupt control register.

A system comprising:

• a control processor and a memory coupled to each other by a main bus;
• a protocol engine coupled to the main bus, the protocol engine having an interrupt handler including:
• a plurality of interrupt inputs, a normal interrupt output and an error interrupt output, both interrupt outputs being coupled to one or more of the plurality of interrupt inputs,
• an interrupt status queue coupled to one of the plurality of interrupt inputs,
• a status register coupled to the interrupt status queue and to the normal interrupt output, and
• a normal interrupt register coupled to normal interrupt output;
• a vectored interrupt control register coupled to the normal interrupt register;
• and
• an auxiliary bus coupling the vectored interrupt control register to the control processor.