US 2006/0149874 A1 · Method and apparatus of reducing transfer latency in an SOC interconnect

Abstract

Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.

Claims21

Dependent claims

A method for reducing transfer latency in a system on a chip, the system on a chip having a bus master, a bus slave and an arbiter, the bus master, bus slave and arbiter being in electronic communication, the bus slave being configured to respond to a request, comprising:

transmitting, from the bus master to the arbiter, a request having a priority signal, the priority signal being associated with a latency requirement;
reviewing the latency requirement to determine whether to elevate the priority signal;
transmitting, from the arbiter to the bus slave, the request and priority signal;
and
transmitting, from the bus slave to the arbiter, the response to the request and the priority signal.

2 more elements

Dependencies are inferred from the claim text.

Method and apparatus of reducing transfer latency in an SOC interconnect

Life of this patent

Method and apparatus of reducing transfer latency in an SOC interconnect

Life of this patent

Abstract

Claims21