DMA in processor pipeline
AssigneeiVivity, Inc.
InventorsAbdelhafid Zaabab, Aashutosh Joshi, Rajneesh Salnl
Life of this patent
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Abstract
The present technique is an atomic technique that places a triggered operation within a processor pipeline, whereby the processor is stalled until the triggered operation is completed. A processor issues an access operation that will trigger an external block operation. The external operation does not return an access valid until the operation is complete.
Claims12
A method for direct memory access, comprising:
- issuing a DMA instruction that triggers a DMA transfer, wherein the DMA transfer is triggered by a register access operation of a DMA register;
- and
- said register access operation does not return an access valid until the DMA transfer is complete.
A system for data processing, comprising:
- a processor, wherein the processor issues an instruction that triggers an operation transfer;
- a hardware block, wherein the hardware block returns an access valid after the operation transfer is complete;
- and
- a bus coupling the processor and the hardware block.
The system of claim 8 wherein the hardware block is a DMA block.
The system of claim 8 wherein the instruction is a DMA instruction.
The system of claim 8 wherein the operation transfer is a DMA transfer.
A method for data processing, comprising:
- issuing an access operation that triggers a hardware operation,
- wherein the hardware operation does not return an access valid until the operation is complete.
A method for data processing, comprising:
- issuing an access operation that triggers a second operation stalls a process until an access valid is returned,
- wherein the access valid is generated after the second operation is complete.
The method of claim 13 wherein the second operation is a DMA transfer operation.
The method of claim 13 wherein the access operation is a DMA instruction.
Dependencies are inferred from the claim text.