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US 2006/0149803 A1Published application
Multipurpose functional unit with multiply-add and format conversion pipeline
AssigneeNVIDIA Corporation
InventorsMing Siu, Stuart Oberman
Life of this patent
Estimating the term…
Abstract
A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and logical test operations.
Claims21
A multipurpose functional unit for a processor, the functional unit comprising:
- an input section configured to receive first, second, and third operands and an opcode designating one of a plurality of supported operations to be performed and further configured to generate a plurality of control signals in response to the opcode;
- a multiplication pipeline coupled to the input section and configurable, in response to the control signals, to compute a product of the first and second operands and to select the computed product as a first intermediate result;
- an addition pipeline coupled to the multiplication section and the test pipeline and configurable, in response to the control signals, to compute a sum of the first and second intermediate results and to select the computed sum as an operation result;
- an exponent pipeline coupled to the input section and configurable, in response to the control signals, to perform an exponent computation on one or more of the first, second, and third operands and to select a result of the exponent computation as an exponent result;
- and
- an output section coupled to receive the operation result and the exponent result and configurable, in response to the control signals, to generate a final result for the one of the supported operations designated by the opcode,
- wherein the plurality of supported operations includes a multiply-add (MAD) operation that operates on the first, second and third operands and a format conversion operation that converts the first operand from an input format to a target format.
4 more elements
A microprocessor comprising:
- an execution core including a plurality of functional units configured to execute program operations,
- wherein the plurality of functional units includes a multipurpose functional unit capable of executing a plurality of supported operations including at least a multiply-add (MAD) operation that operates on the first, second and third operands and a format conversion operation that converts the first operand from an input format to a target format,
- wherein the multipurpose functional unit includes:
- an input section configured to receive first, second, and third operands and an opcode designating one of a plurality of supported operations to be performed and further configured to generate a plurality of control signals in response to the opcode;
- a multiplication pipeline coupled to the input section and configurable, in response to the control signals, to compute a product of the first and second operands and to select the computed product as a first intermediate result;
- an addition pipeline coupled to the multiplication section and the test pipeline and configurable, in response to the control signals, to compute a sum of the first and second intermediate results and to select the computed sum as an operation result;
- an exponent pipeline coupled to the input section and configurable, in response to the control signals, to perform an exponent computation on one or more of the first, second, and third operands and to select a result of the exponent computation as an exponent result;
- and
- an output section coupled to receive the operation result and the exponent result and configurable, in response to the control signals, to generate a final result for the one of the supported operations designated by the opcode.
6 more elements
A method of operating a functional unit of a microprocessor, the method comprising:
- receiving an opcode designating one of a plurality of supported operations to be performed and one or more operands on which the designated operation is to be performed;
- in response to the opcode and the one or more operands, operating a multiplication pipeline in the functional unit to generate a first intermediate result and a second intermediate result;
- in response to the opcode and the one or more operands, operating a test pipeline in the functional unit to generate a second intermediate result;
- operating an exponent pipeline in the functional unit to generate an exponent result and an alignment control signal;
- and
- operating an addition pipeline in the functional unit in response to the alignment control signal to add the first and second intermediate results and generate an operation result,
- wherein the plurality of supported operations includes at least a multiply-add (MAD) operation that operates on the first, second and third operands and a format conversion operation that converts the first operand from an input format to a target format.
4 more elements
Dependencies are inferred from the claim text.