Semiconductor device having a mode of functional test

A semiconductor device having an access time measuring test mode, comprising:

• a circuit block to which an input signal is input at a timing in accordance with an input clock, and which outputs an output signal having a value corresponding to the input signal;
• an operational path for latching the output signal of said circuit block during a normal operation;
• a dummy latch for latching the output signal of said circuit block during a test operation;
• a first signal path for guiding a test input signal, which has been supplied to a first pad, to a signal input terminal of said circuit block;
• a second signal path for guiding a test clock, which has been supplied to a second pad, to a clock input terminal of said circuit block;
• a third signal path for guiding the output signal from a signal output terminal of said circuit block to an input terminal of said operational latch;
• a fourth signal path for guiding the output signal from the signal output terminal of said circuit block to an input terminal of said dummy latch,
• a fifth signal path for guiding a latched signal output from a signal terminal of said dummy latch to a third pad;
• and
• a sixth signal path for guiding the output signal from the signal output terminal of said circuit block to a fourth pad,
• wherein said dummy latch is constituted so that an access time from when said dummy latch has the output signal of said circuit block input thereto to when said dummy latch outputs the latched signal, is substantially equal to an access time of said operational latch, and
• wherein said third and fourth signal paths are formed so that a wiring delay time from the signal output terminal of said circuit block to the input terminal of said dummy latch is substantially equal to a wiring delay time from the signal output terminal of said circuit block to the input terminal of said operational latch.