Secure controller for block oriented storage
OwnerDennis O'Connor, Mark Fullerton +1inventors
InventorsDennis O'Connor, Mark Fullerton, Ray Richardson
Life of this patent
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Abstract
A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.
Claims23
A storage controller comprising a command pointer register to point to a chain of commands, the command pointer register having at least one bit to signify the security status of a first command of the chain of commands.
An integrated circuit comprising:
- a processor;
- and
- a storage controller including a mechanism to partition a storage device into secure and non-secure partitions, and including a command pointer register to point to a chain of commands in memory, the command pointer register having a secure/non-secure bit to indicate a security status of a first command in the chain of commands.
A method comprising:
- executing a chain of commands pointed to by a command pointer register in a storage controller, wherein each command in the chain of commands includes a secure/non-secure bit;
- and
- performing exception processing if a first command in the chain of commands is non-secure and a subsequent command in the chain of commands is secure.
A system comprising:
- an antenna;
- a receiver coupled to the antenna;
- and
- an integrated circuit coupled to the receiver, the integrated circuit including a processor, a storage controller including a mechanism to partition a storage device into secure and non-secure partitions, and including a command pointer register to point to a chain of commands in memory, the command pointer register having a secure/non-secure bit to indicate the status of a first command in the chain of commands, and a bus interconnecting the processor and the storage controller, the bus including a signal path to identify a security status of a storage controller transaction.
Dependencies are inferred from the claim text.