Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design

A method of reticle field-wide hierarchy management in an integrated circuit chip layout design, the method comprising the steps of:

• receiving a chip layout in hierarchical form;
• receiving placement information for the chip layout across a reticle field;
• and
• generating templates and building a litho hierarchy tree for the entire reticle field in accordance with the placement information.

A method of partitioning a plurality of instances of a template candidate cell in a hierarchical chip layout design, the method comprising:

• identifying adjacent regions for each of the instances of the template candidate cell;
• generating proximity environment definitions for the instances of the template candidate cell, said proximity environment definitions comprising one or more primitive unit cells (PUC's) overlapping or in contact with the adjacent regions of each of the instances;
• determining a set of unique environments from the proximity environment definitions;
• and
• assigning the instances of the template candidate cell to corresponding ones of the unique environments based on the PUC's.

A computer software product for distributing a computational task for an integrated circuit layout design on a reticle field wide basis among a collection of networked computation nodes, the product comprising a computer-readable medium in which program instructions are stored, which instructions, when read by a computer, cause the computer to:

• generate a plurality of templates building a litho hierarchy tree for the entire reticle field in accordance with the placement information of the chip layout across the reticle field;
• assign the computation tasks for the templates to the networked computation nodes for concurrent execution;
• and
• assemble outputs from the computation nodes.