Video processing architecture definition by function graph methodology
AssigneeMicronas USA, Inc.
InventorsLi Sha, Weimin Zeng
Life of this patent
Estimating the term…
Abstract
A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.
Claims20
A method for designing video processing architecture in accordance with a video processing a particular specification, comprising:
- generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or inter-node-communication;
- generating a hardware architecture design for a video processing application;
- comparing the hardware architecture design to the function graph to determine if the design complies with the function graph;
- and
- in response to determining the hardware architecture design complies with the functional graph, providing a final architecture for register transfer level (RTL) implementation.
A method for designing video processing architecture in accordance with a video processing a particular specification, comprising:
- generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or inter-node-communication;
- generating a hardware architecture design for a video processing application;
- comparing the hardware architecture design to the function graph to determine if the design complies with the function graph;
- in response to determining the hardware architecture design complies with the functional graph, providing a final architecture;
- in response to determining the hardware architecture design does not comply with the functional graph, allowing adjustment to the hardware architecture design as necessary;
- performing register transfer level (RTL) implementation of the final architecture;
- and
- comparing the RTL implementation to a C-model derived from the specification to determine if the RTL implementation complies with the C-model;
- and
- in response to determining the RTL implementation does not comply with the C-model, allowing adjustment to the RTL implementation as necessary.
A system for designing video processing architecture in accordance with a video processing a particular specification, comprising:
- a function graph module for generating a function graph that graphically represents criteria of the specification, the function graph having input from an external source and providing output to an external target, and including a plurality of functional nodes each for performing a specific data processing function, one or more data elements input to and/or output from a functional node, inter-node communication between the functional nodes, and control information provided by a functional node to control another functional node or inter-node-communication;
- a hardware architecture design module for generating a hardware architecture design for a video processing application;
- and
- an architecture verification module for comparing the hardware architecture design to the function graph to determine if the design complies with the function graph, and if so, for providing a final architecture for register transfer level (RTL) implementation.
Dependencies are inferred from the claim text.