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US 2006/0143551 A1Published application
Localizing error detection and recovery
AssigneeIntel Corporation
InventorsArijit Biswas, Steven Raasch, Shubhendu Mukherjee, Subhasish Mitra
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Abstract
In one embodiment, the present invention includes a method of detecting and correcting an error by detecting the error in a circuit coupled to a first stage of a semiconductor device, and correcting the error in the circuit using valid data present in the circuit. The circuit may be a scan cell, in some embodiments. In such manner, errors may be corrected locally, minimizing the impact of the error on performance and power consumption. Other embodiments are described and claimed.
Claims24
A method comprising:
- detecting an error in a scan cell coupled to a first stage of a semiconductor device;
- and
- correcting the error in the scan cell using valid data present in the scan cell.
An apparatus comprising:
- a first circuit coupled to receive an output of a multiplexer, the first circuit to be clocked by a first clock;
- and
- a second circuit to receive incoming data, the second circuit to be clocked by the first clock, the multiplexer to receive the incoming data and an output of the second circuit, the multiplexer to output the incoming data or the output of the second circuit.
A system comprising:
- a processor having a first stage and a second stage;
- an error circuit coupled between the first stage and the second stage to detect an error, the error circuit comprising:
- a data path to receive an output of the first stage, the data path to be clocked by a first clock;
- a scan path to receive the output of the first stage, the scan path to be clocked by the first clock;
- and
- a dynamic random access memory coupled to the processor.
3 more elements
Dependencies are inferred from the claim text.